Logical calculation circuit, logical calculation device, and logical calculation method

ABSTRACT

A logical calculation circuit capable of storing data, and performing logical calculations with high reliability and high speeds are provided. The residual polarized state s′ of a load ferroelectric capacitor Cs′ is actively changed so that the residual polarized state s′ of a load ferroelectric capacitor Cs′ is opposite to the residual polarized state s of a storage ferroelectric capacitor Cs. In the case a reference potential is made c=0 in the calculation operation, even if the second data to be calculated x=1 is given to the storage ferroelectric capacitor Cs in the residual polarized state s (the first data to be calculated)=0, the ferroelectric capacitor Cs does not reverse in polarity. Even with combinations other than s=0 and x=1, the ferroelectric capacitor Cs does not reverse in polarity. Difference is great between a potential VA=VA(0) occurring at a coupling node when x=1 is given to the ferroelectric capacitor Cs of s=0 and a potential VA=VA(1) occurring at the coupling node when x=1 is given to the ferroelectric capacitor Cs of s=1.

CROSS-REFERENCE TO RELATED APPLICATIONS

The whole disclosure of JP-A-2003-29165 (Applied on Feb. 6, 2003)including its specification, claims, drawings, and abstract isincorporated herein by reference.

TECHNICAL FIELD

This invention relates to a logical calculation circuit, a logicalcalculation device, and a logical calculation method, in particularrelates to those using non-volatile memory elements such asferroelectric capacitors.

BACKGROUND ART

The non-volatile memory is known as a circuit using ferroelectriccapacitors. Using ferroelectric capacitors makes it possible tofabricate a rewritable non-volatile memory that works at a low voltage(for example refer to FIG. 3 of JP-2674775).

However, although such a conventional circuit can be used to store data,it cannot be used to perform logical calculation of data.

DISCLOSURE OF THE INVENTION

An object of this invention is to provide a logical calculation circuit,a logical calculation device, and a logical calculation method, usingferroelectric capacitors, that make it possible to store data andperform logical calculation of data, while solving the above-mentionedproblem accompanying the conventional circuit. Another object of thisinvention is to provide the logical calculation circuit, the logicalcalculation device, and the logical calculation method, that are capableof performing numerical calculations with high reliability at highspeeds.

A logical calculation circuit of this invention includes: a storageferroelectric capacitor for retaining a polarized state corresponding toa first data to be calculated and having first and second terminals; aload ferroelectric capacitor for retaining a polarized statecorresponding to the first data to be calculated and substantiallycomplementary to the polarized state of the storage ferroelectriccapacitor, and having a third terminal connected to the first terminalof the storage ferroelectric capacitor, and a fourth terminal; and acalculation result output section connected to a coupling node to outputa logical calculation result of the first and second data to becalculated for a specified logical operator according to a potential, ofthe coupling node between the first terminal of the storageferroelectric capacitor and the third terminal of the load ferroelectriccapacitor, obtained by connecting the fourth terminal of the loadferroelectric capacitor to a specified reference potential and by givinga second data to be calculated to the second terminal of the storageferroelectric capacitor.

The logical calculation circuit of this invention includes: anon-volatile memory element for retaining non-volatile statecorresponding to a binary data, a first data to be calculated s, andhaving first and second terminals; a non-volatile load element forretaining non-volatile state corresponding to a binary, second data tobe calculated /s, an inverted value of the first data to be calculateds, having a third terminal connected to the first terminal of thenon-volatile memory element, and a fourth terminal; and a calculationresult output section for outputting a logical calculation result of thefirst and second data to be calculated s and x, as a calculation resultdata z as a binary data for a specified logical operator correspondingto a reference potential according to the states of the non-volatilememory element and the non-volatile load element obtained bypre-charging the coupling node between the first terminal of thenon-volatile memory element and the third terminal of the non-volatileload element to the reference potential and then giving the second datax as a binary data to the second terminal of the non-volatile memoryelement while maintaining the fourth terminal of the non-volatile loadelement at a reference potential arbitrarily chosen out of twocomplementary reference potentials, in which logical calculation circuitis constituted that the calculation result data z substantially meetsthe following equation when the binary data corresponding to the twocomplementary reference potentials are assumed to be c and /c,z=/c AND x AND /s OR c AND (x OR /s).

A logical calculation circuit of this invention includes: a non-volatilememory element for retaining non-volatile state corresponding to thefirst data to be calculated, a non-volatile load element for retainingnon-volatile state of different state change rate depending on the firstdata to be calculated and connected to the non-volatile memory elementthrough a coupling node, and a calculation result output section foroutputting a logical calculation result of the first and second data tobe calculated for a specified logical operator based on the state changeamount of both the non-volatile memory element and the non-volatile loadelement obtained by giving the second data to be calculated to thenon-volatile memory element.

A logical calculation method of this invention is a method of performinglogical calculation using the first and second data to be calculated fora specified logical operator including: writing step of preparing anon-volatile memory element for retaining non-volatile statecorresponding to the first data to be calculated and having the firstand second terminals; and a non-volatile load element for retainingnon-volatile state of different state change rate depending on the firstdata to be calculated and having the third terminal connected to thefirst terminal of the non-volatile memory element through the couplingnode, and the fourth terminal; and a reading step of performing logicalcalculation based on the state change amounts of both the non-volatilememory element and the non-volatile load element obtained by connectingthe fourth terminal of the non-volatile load element to a specifiedreference potential and by giving the second data to be calculated tothe second terminal of the non-volatile memory element.

While the features and constitution of this invention are broadlydescribed above, their details together with objects will become moreapparent with the following disclosure in reference to appendeddrawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram of a logical calculation circuit 1 according to afirst embodiment of the invention.

FIG. 2 is an example timing chart of operations of the logicalcalculation circuit 1.

FIGS. 3A and 3B are respectively circuit diagrams for explaining a datawrite operation (WO) and a standby state (Standby).

FIGS. 4A and 4B are respectively a hysteresis diagram and a statetransition diagram for explaining the data write operation of thelogical calculation circuit 1.

FIGS. 5A-5C are circuit diagrams for explaining the data read operation(RO) of the logical calculation circuit 1.

FIGS. 6A and 6B are respectively a hysteresis diagram and a truth tablefor explaining the data read operation of the logical calculationcircuit 1 when the reference potential c=0 corresponding to a logicaloperator.

FIGS. 7A and 7B are respectively a hysteresis diagram and a truth tablefor explaining the data read operation of the logical calculationcircuit 1 when the reference potential c=1 corresponding to the logicaloperator.

FIGS. 8A and 8B are respectively an equivalent circuit and a symboldiagram of the logical calculation circuit 1.

FIG. 9 is a diagram of a logical calculation circuit 21 according toanother embodiment of the invention.

FIG. 10 is a timing chart for performing logical calculation using thedata write operation of the logical calculation circuit 21.

FIGS. 11A and 11C are respectively an equivalent circuit and a symboldiagram of the logical calculation circuit 21 assuming s=1 in thes-initializing operation of the example of FIG. 10. FIGS. 11B and 11Dare respectively an equivalent circuit and a symbol diagram of thelogical calculation circuit 21 assuming s=0 in the s-initializingoperation of the example of FIG. 10.

FIG. 12 is a timing chart for performing logical calculation using thedata read operation of the logical calculation circuit 21.

FIGS. 13A and 13C are respectively an equivalent circuit and a symboldiagram of the logical calculation circuit 21 assuming the referencepotential c=0 in the example of FIG. 12. FIGS. 13B and 13D arerespectively an equivalent circuit and a symbol diagram of the logicalcalculation circuit 21 assuming the reference potential c=1 in theexample of FIG. 12.

FIG. 14 is another example timing chart for performing logicalcalculation using the data read operation of the logical calculationcircuit 21.

FIGS. 15A, 15B, and 15C respectively show the polarized states of theferroelectric capacitor Cs and the ferroelectric capacitor Cs′ of theexample shown in FIG. 14 respectively in initializing operation (Init.),calculating operation (Op.), and restoring operation (Res.)

FIG. 16A is a diagram of a logical calculation circuit 31 according tostill another embodiment of the invention. FIG. 16B shows the logicalcalculation circuit 31 indicated with symbols.

FIG. 17 is an example timing chart of the operation of the logicalcalculation circuit 31.

FIGS. 18A, 18B, and 18C are circuit diagrams for explaining respectivelythe data write operation (WO), the initializing operation in the dataread operation (Init., RO), and the calculation operation in the dataread operation (Op., RO) of the logical calculation circuit 31.

FIGS. 19A and 19B are respectively circuit diagrams for explaining therestoration operation in data reading operation (Res., RO) and standbystate (Standby) of the logical calculation circuit 31.

FIG. 20 is a block diagram of a logical calculation device, a contentaddressable memory 41, utilizing the logical calculation circuit 31.

FIG. 21 is a diagram of a word circuit 46 constituted using logicalcalculation circuits 53, 55, . . . similar to the logical calculationcircuit 31.

FIG. 22A is a circuit diagram of a CAM cell (content addressable memorycell) 51 made up of components, a pair of logical calculation circuits53 and 55. FIG. 22B shows the CAM cell 51 expressed as a logicalcircuit.

FIG. 23 is a timing chart of the operation of the CAM cell 51.

FIG. 24 is a block diagram of a content addressable memory 61, a logicalcalculation device utilizing the logical calculation circuit 31 above.

FIG. 25 is a diagram of a word circuit 66 constituted using logicalcalculation circuits 73, 75, . . . similar to the logical calculationcircuit 31.

FIG. 26A is a circuit diagram of a CAM cell 71 made up of components, apair of logical calculation circuits 73 and 75. FIG. 26B shows the CAMcell 71 expressed as a logical circuit.

FIG. 27 is a timing chart of the operation of the CAM cell 71.

FIG. 28A shows a logical calculation circuit 81 in still anotherembodiment of the invention. FIG. 28B is a symbol diagram of the logicalcalculation circuit 81.

FIG. 29 is an example timing chart of the operations of the logicalcalculation circuit 81.

FIGS. 30A and 30B are respectively circuit diagrams for explaining thereset operation (Reset) and data write operation (WO) of the logicalcalculation circuit 81.

FIGS. 31A and 31B are respectively circuit diagrams for explaining thedata read operation (RO) of the logical calculation circuit 81.

FIG. 32 is an example block diagram of a pipelined logical calculationdevice 91 using a plural number of logical calculation circuits.

FIG. 33 is an example timing flowchart of the operations of thepipelined logical calculation device 91.

FIG. 34 is a block diagram of constitution of the pipelined logicalcalculation device of FIG. 32 embodied as a full adder 101.

FIG. 35 is an equivalent circuit diagram of the full adder 101 expressedas a logical circuit.

FIG. 36 is an example block diagram of a pipelined multiplier using aplural number of the full adder 101 of FIG. 34 as element calculationdevices.

FIG. 37 is a block diagram of constitution of an adder unit 119.

FIG. 38 is an example constitution of a pipelined multiplier ofseries-parallel type using the logical calculation circuit 81 shown inFIG. 28A.

FIG. 39 is an explanatory diagram of the operations of a pipelinedmultiplier 141.

FIG. 40 is a block diagram of constitution of the second levelcalculation section 141 b of the pipelined multiplier 141.

FIG. 41 shows a logical circuit constitution of the second levelcalculation section 141 b.

FIG. 42A is an example circuit diagram of a non-volatile load elementusing paraelectric capacitor. FIG. 42B is a hysteresis diagram forexplaining the data read operation of the logical calculation circuit 31using a load element 121 as the non-volatile load element.

FIG. 43A shows an equivalent circuit of the load element 121 in the dataread operation (RO) when y=0 is given to the bit line BL2 in the datawrite operation (WO) of FIG. 17. FIG. 43B shows an equivalent circuit ofthe load element 121 in the data read operation (RO) when y=1 is givento the bit line BL2 in the data write operation (WO) of FIG. 17.

FIG. 44A is another example circuit diagram of a non-volatile loadelement using a paraelectric capacitor. FIG. 44B is a hysteresis diagramfor explaining data read operation of the logical calculation circuit 31using a load element 131 as the non-volatile load element.

FIG. 45A shows an equivalent circuit of the load element 131 in the dataread operation (RO) when y=0 is given to the bit line BL2 in the datawrite operation (WO) of FIG. 17. FIG. 45B shows an equivalent circuit ofthe load element 131 in the data read operation (RO) when y=1 is givento the bit line BL2 in the data write operation (WO) of FIG. 17.

FIG. 46A is an example circuit diagram of a non-volatile memory elementusing dielectric capacitors. FIG. 46B is a diagram for explaining thedata read operation of the logical calculation circuit 31 using a memoryelement 151 as the non-volatile memory element.

FIG. 47A shows an equivalent circuit of the load element 151 in the dataread operation (RO) when y=0 is given to the bit line BL1 in the datawrite operation (WO) of FIG. 17. FIG. 47B shows an equivalent circuit ofthe load element 151 in the data read operation (RO) when y=1 is givento the bit line BL1 in the data write operation (WO) of FIG. 17.

FIG. 48A is another example circuit diagram of a non-volatile memoryelement using paraelectric capacitors. FIG. 48B is a diagram forexplaining the data read operation of the logical calculation circuit 31using a memory element 161 as the non-volatile memory element.

FIG. 49A shows an equivalent circuit of the memory element 161 in thedata read operation (RO) when y=0 is given to the bit line BL1 in thedata write operation (WO) of FIG. 17. FIG. 49B shows an equivalentcircuit of the memory element 161 in the data read operation (RO) wheny=1 is given to the bit line BL1 in the data write operation (WO) ofFIG. 17.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a diagram of a logical calculation circuit 1 according to afirst embodiment of the invention. The logical calculation circuit 1includes: a ferroelectric capacitor Cs as a storage ferroelectriccapacitor (non-volatile memory element), a ferroelectric capacitor Cs′as a load ferroelectric capacitor (non-volatile load element), atransistor MP as an output transistor (calculation result outputsection) and transistors M1, M2, and Mw.

The ferroelectric capacitors Cs and Cs′ are made to have substantiallythe same hysteresis characteristics and exhibit complementary residualpolarized states. The transistors MP, M1, M2, and Mw are all N-channelMOSFETs (metal oxide semiconductor field effect transistors).

The first terminal 3 of the ferroelectric capacitor Cs is connectedthrough a coupling node 11 to the third terminal 7 of the ferroelectriccapacitor Cs′. The second terminal 5 of the ferroelectric capacitor Csis connected to a bit line BL1. The fourth terminal 9 of theferroelectric capacitor Cs′ is connected to a bit line BL2.

The coupling node 11 is connected to the gate terminal of the transistorMP. The coupling node 11 is also connected through the transistor Mw toa bit line BLw. The gate terminal of the transistor Mw is connected to awriting control line WL.

The coupling node 11 is connected through the transistors M1 and M2respectively to the bit lines BL1 and BL2. The gate terminals of thetransistors M1 and M2 are both connected to a reading control line RL.The input terminal of the transistor MP is given an input signal Z1. Theoutput signal of the transistor MP is assigned as Z2.

In the data write operation (WO), a third data to be calculated y1 isgiven to the bit line BLw, and a fourth data to be calculated y2 isgiven to the bit lines BL1 and BL2. In the data read operation (RO), areference potential c corresponding to a specified logical operator isgiven to the bit lines BL1 and BL2, and a second calculation data x isgiven to the bit line BL1.

Next, the operation of the logical calculation circuit 1 shown in FIG. 1is described. FIG. 2 is an example timing chart of operations of thelogical calculation circuit 1. FIGS. 3A and 3B are respectively circuitdiagrams for explaining data write operation (WO) and standby state(Standby). FIGS. 4A and 4B are respectively a hysteresis diagram and astate transition diagram for explaining the data write operation of thelogical calculation circuit 1.

FIGS. 5A-5C are circuit diagrams for explaining the data read operation(RO) of the logical calculation circuit 1. FIGS. 6A and 6B arerespectively a hysteresis diagram and a truth table for explaining thedata read operation of the logical calculation circuit 1 when thereference potential c=0 corresponding to the logical operator.

FIGS. 7A and 7B are respectively a hysteresis diagram and a truth tablefor explaining the data read operation of the logical calculationcircuit 1 when the reference potential c=1 corresponding to the logicaloperator. FIGS. 8A and 8B are respectively an equivalent circuit and asymbol diagram of the logical calculation circuit 1.

As shown in FIG. 2, in the data write operation (WO), the control linesWL and RL are respectively given “1” (or a power source potential Vdd asthe second reference potential) and “0” (or the ground potential GND asthe first reference potential). The bit line BLw is given the third datato be calculated y1. The bit lines BL1 and BL2 are given the fourth datato be calculated y2. In this embodiment, it is assumed that y1=1 andy2=0.

In the data write operation (WO) as shown in FIG. 3A, the transistorsMw, M1, and M2 are on, off, and off, respectively. Therefore, y1=1 isgiven to the coupling node 11, while y2=0 is given to the secondterminal 5 of the ferroelectric capacitor Cs and to the fourth terminal9 of the ferroelectric capacitor Cs′.

In the succeeding standby state (Standby) as shown in FIG. 3B, thetransistors Mw, M1, and M2 are off, on, and on, respectively. Therefore,the coupling node 11, the second terminal 5 of the ferroelectriccapacitor Cs, and the fourth terminal 9 of the ferroelectric capacitorCs′ are at the same potential. Therefore, when the circuit operationshifts from data writing to standby, the polarized state of theferroelectric capacitor Cs becomes the residual polarized state at thepoint s=0 as shown in FIG. 4A.

Contrary to the above, when the third data to be calculated y1=0 and thefourth data to be calculated y2=1 are given in the data write operation,the polarized state of the ferroelectric capacitor Cs becomes theresidual polarized state at the point s=1 in the succeeding standbystate (Standby).

By the data write operation, the residual polarized state s of theferroelectric capacitor Cs changes as shown in FIG. 4B. That is, in thecase the residual polarized state of the ferroelectric capacitor Csbefore the write operation is s=1, the residual polarized state s=1 ofthe ferroelectric capacitor Cs remains unchanged when the third data tobe calculated y1 and the fourth data to be calculated y2 are (y1,y2)=(0, 0), (0, 1), or (1, 1). However, when (y1, y2)=(1, 0), theresidual polarized state of the ferroelectric capacitor Cs is changed tos=0 by the write operation.

On the other hand, in the case the residual polarized state of theferroelectric capacitor Cs before the data write operation is s=0, theresidual polarized state s=0 of the ferroelectric capacitor Cs remainsunchanged when the third data to be calculated y1 and the fourth data tobe calculated y2 are (y1, y2)=(0, 0), (1, 0), or (1, 1). However, when(y1, y2)=(0, 1), the residual polarized state of the ferroelectriccapacitor Cs is changed to s=1 by the write operation.

Assuming the residual polarized state of the ferroelectric capacitor Csimmediately before the write operation to be sb, the residual polarizedstate s (the first data to be calculated) of the ferroelectric capacitorCs may be expressed with the following equation.s=/sb AND /y1 AND y2 OR sb AND (/y1 OR y2)

In this way, it is possible to perform logical calculation utilizing thedata write operation to the ferroelectric capacitor Cs. Incidentally,the residual polarized state s′ of the ferroelectric capacitor Cs′ showsopposite (in complementary relationship) to the residual polarized states of the ferroelectric capacitor Cs.

Referring back to FIG. 2, the data write operation (WO) is followed bythe data read operation (RO). The data read operation (RO) is performedin the order of an initializing operation (Init.), calculation operation(Op.) and a restoring operation (Res.).

As shown in FIG. 2, in the initializing operation (Init.), the controllines WL and RL are respectively given “0” and “1”. Further, a referencepotential c corresponding to a specified logical operator is given tothe bit lines BL1 and BL2. In this embodiment, c=0.

As shown in FIG. 5A, in the initializing operation (Init.), thetransistors Mw, M1, and M2 are off, on, and on, respectively. Therefore,c=0 is given to the second terminal 5 of the ferroelectric capacitor Csand to the fourth terminal 9 of the ferroelectric capacitor Cs′.

The initializing operation allows the coupling node 11 to be pre-chargedto the reference potential c corresponding to a specified logicaloperator without changing the residual polarized states s and s′ of theferroelectric capacitor Cs and the ferroelectric capacitor Cs′.

In a succeeding calculation operation (Op.) as shown in FIG. 2, thecontrol lines WL and Rl are respectively given “0” and “0”. Further, thesecond data to be calculated x and the reference potential c above aregiven respectively to the bit lines BL1 and BL2. In this embodiment,x=1, and c=0.

In the calculation operation (Op.) as shown in FIG. 5B, all thetransistors Mw, M1, and M2 are off. Therefore, x=1 and c=0 arerespectively given to the second terminal 5 of the ferroelectriccapacitor Cs and to the fourth terminal 9 of the ferroelectric capacitorCs′.

As described above, because the ferroelectric capacitor Cs is in thepolarized state indicated with s=0, the ferroelectric capacitor Cs′ isin the polarized state indicated with s′=1. By graphical determinationmethod using the graph of FIG. 6A here, the potential generated at thecoupling node 11 by the calculating operation (Op.) is determined asVA=VA(0). Because the potential VA(0) is greater than the thresholdvoltage Vth of the transistor MP, the transistor MP turns on. In otherwords, as shown in FIG. 2, the output signal of the transistor MPbecomes Z2=Z1.

In contrast to the above, in the case the residual polarized state ofthe ferroelectric capacitor Cs in the data write operation is s=1, thepotential generated at the coupling node 11 in the calculation operation(Op.) is VA=VA(1) as shown in FIG. 6A. Because the potential VA(1) issmaller than the threshold voltage Vth of the transistor MP, thetransistor MP turns off. In other words, the output signal of thetransistor MP becomes Z2=NC (disconnected state).

In the case the second data to be calculated in the data read operationis made x=0, the transistor MP turns off regardless of the residualpolarized state of the ferroelectric capacitor Cs. Therefore, theresults of the calculation operations (Op.) with the reference potentialc are summarized in the truth table as shown in FIG. 6B.

On the other hand, when the reference potential c=1, the potential VAgenerated at the coupling node 11 in the calculation operation (Op.) maybe determined using the graph of FIG. 7A. Results of calculationoperations (Op.) in this case may be summarized in the truth table asshown in FIG. 7B.

Assuming on and off states of the transistor MP to correspond to z=1 andz=0, these states may be expressed as follows:z=/c AND x AND /s OR c AND (x OR /s)

In this way, the operations of reading data from the ferroelectriccapacitor Cs may be used to perform logical calculations.

As described above, this logical calculation circuit 1 may be used toperform logical calculations by using data write operation (WO) and dataread operation (RO) while storing data in the ferroelectric capacitor Csin non-volatile state. The logical calculation circuit 1 may beexpressed with an equivalent logical circuit as shown in FIG. 8A. Of theequivalent logical circuit of FIG. 8A, the part 13 is the logicalcalculation section using the data write operation (WO) and the part 15is the logical calculation section using the data read operation (RO).Further, the logical calculation circuit 1 may be expressed as FIG. 8Busing symbols.

Now, in the logical calculation circuit 1, as described above, the loadelement is the ferroelectric capacitor Cs′ having nearly the samehysteresis characteristic as that of the storage ferroelectric capacitorCs. And that, the residual polarized state of the load ferroelectriccapacitor Cs′ is actively changed to be opposite to that of the storageferroelectric capacitor Cs.

Therefore, in the case the reference potential is made c=0 in thecalculation operation (Op.), as shown in FIG. 6A, even if the seconddata to be calculated x=1 is given to the storage ferroelectriccapacitor Cs in the residual polarized state s=0, the ferroelectriccapacitor Cs does not reverse in polarity. As a matter of course, theferroelectric capacitor Cs cannot reverse in polarity with any othercombination than the residual polarized state s=0, and the second datato be calculated x=1.

Also in the case the reference potential is made c=1 in the calculationoperation (Op.), as shown in FIG. 7A, the storage ferroelectriccapacitor Cs cannot reverse in polarity. Likewise, the loadferroelectric capacitor Cs′ cannot reverse in polarity. In other words,the logical calculation circuit 1 permits nondestructive reading.

Further, in the case the reference potential is made c=0 in thecalculation operation (Op.) as shown in FIG. 6A, the difference is verylarge between the potential VA=VA(0) generated at the coupling node 11when the second data to be calculated x=1 is given to the storageferroelectric capacitor Cs in the residual polarized state of s=0, andthe potential VA=VA(1) generated at the coupling node 11 when the seconddata to be calculated x=1 is given to the storage ferroelectriccapacitor Cs in the residual polarized state of s=1.

Likewise, in the case the reference potential is made c=1 in thecalculation operation (Op.) as shown in FIG. 7A, the difference is verylarge between the potential VA=VA(0) generated at the coupling node 11when the second data to be calculated x=0 is given to the storageferroelectric capacitor Cs in the residual polarized state of s=0 andthe potential VA=VA(1) generated at the coupling node 11 when the seconddata to be calculated x=0 is given to the storage ferroelectriccapacitor Cs in the residual polarized state of s=1. In other words, itis seen that the read margin is very large in the data read operation.

Referring again to FIG. 2, in the restoration operation (Res.) performedafter the calculation operation (Op.), “0” and “0” are respectivelygiven to the control lines WL and RL like in the calculation operation.The bit lines BL1 and BL2 are given, contrary to the calculationoperation, respectively the reference potential c=0 and the second datato be calculated x=1.

As shown in 5C, in the restoration operation (Res.) like in thecalculation operation, the transistors Mw, M1, and M2 are all off.Therefore, the second terminal 5 of the ferroelectric capacitor Cs andthe fourth terminal 9 of the ferroelectric capacitor Cs′ arerespectively given c=0 and x=1, contrary to the calculation operation.

As described above, the ferroelectric capacitor Cs and the ferroelectriccapacitor Cs′ are both constituted not to reverse in polarity. However,the calculation operation may cause, although not so much as thepolarity reversal, some distortion in the hysteresis characteristics ofthe ferroelectric capacitor Cs and the ferroelectric capacitor Cs′.

To correct this distortion, it is adapted that, in the restorationoperation, a voltage of opposite direction to that in the calculationoperation is given to a compound ferroelectric capacitor made by seriesconnection of the ferroelectric capacitor Cs and the ferroelectriccapacitor Cs′.

Next, FIG. 9 shows a logical calculation circuit 21 as anotherembodiment of this invention. The logical calculation circuit 21 is madeby adding transistors M3 and M4 to the logical calculation circuit 1described above.

The input terminal of the transistor MP is connected through thetransistor M3 to the ground potential GND. The output terminal of thetransistor MP is connected to the output line ML. The output line ML isconnected through the transistor M4 to the second reference potential,which is the power source potential Vdd. The gate terminals of thetransistors M3 and M4 are connected to a preset line PRE.

The transistor M3 is an N-channel MOSFET (metal oxide semiconductorfield effect transistor). The transistor M4 is a P-channel MOSFET (metaloxide semiconductor field effect transistor).

FIG. 10 is a timing chart for performing logical calculation using thedata write operation of the logical calculation circuit 21. Operation ofwrite logical calculation using the logical calculation circuit 21 isdescribed in reference to FIG. 10. The write logical calculation isperformed as shown in FIG. 10 in the order of data write operation (WO)and data read operation (RO).

The data write operation (WO) is performed in the order of s-initializeoperation (Write s=1) and write calculation operation (Wop.). First, inthe s-initialize operation (Write s=1), the control lines WL and RL arerespectively given “1” and “0”. The bit line BLw is given “0”. The bitlines BL1 and BL2 are given “1”.

As a result, the residual polarized state of the ferroelectric capacitorCs is initialized to s=1. Naturally, the residual polarized state of theferroelectric capacitor Cs′ is initialized to s′=0. With thes-initialize operation, it is possible to determine a logical operatorin the succeeding write calculation operation (Wop.).

In the write calculation operation (Wop.) after the s-initializeoperation (Write s=1), the control lines WL and RL are respectivelygiven “1” and “0”. The bit line BLw is given the third data to becalculated, y1. The bit lines BL1 and BL2 are given the fourth data tobe calculated, y2. Here, it is assumed that y1=0 and y2=0. With thisoperation, the residual polarized state s of the ferroelectric capacitorCs and the residual polarized state s′ of the ferroelectric capacitorCs′ are updated.

In other words, the following calculation is performed by the data writeoperation (WO) and the result is stored.s=/sb AND /y1 AND y2 OR sb AND (/y1 OR y2)

In the example of FIG. 10, as the s-initialize operation (Write s=1)makes sb=1, the above equation may be expressed ass=/y1 OR y2.

The succeeding data read operation (RO) is performed in order of aninitialize operation (Init.) followed by a calculation operation (Op.).In the initialize operation (Init.), the control lines WL and RL arerespectively given “0” and “1”. The bit lines BL1 and BL2 are given thereference potential c=0.

The above operation allows the coupling node 11 to be pre-charged withthe reference potential c corresponding to a specified logical operatorwithout changing the residual polarized states s and s′ of theferroelectric capacitors Cs and Cs′.

In the calculation operation (Op.) performed after the initializeoperation (Init.), as shown in FIG. 10, the control lines WL and RL arerespectively given “0” and “0”. The bit lines BL1 and BL2 arerespectively given x=1 and c=0. With this operation, the transistor MPturns on or off according to the potential occurring at the couplingnode 11.

Assuming the on and off states of the transistor MP to correspond to z=1and z=0, they are expressed as follows.z=/c AND x AND /s OR c AND (x OR /s)

In the example of FIG. 10, as the s-initialize operation (Init.) and thecalculation operation (Op.) make x=1 and c=0, the above equation isexpressed as follows.z=/s

Putting the calculation contents of the data write operation (WO) intothe above equation, the example of FIG. 10 is to perform the followingcalculation.z=/(/y1 OR y2)=y1 AND /y2

FIGS. 11A and 11C are respectively the equivalent circuit and symbolicdiagram of the logical calculation circuit 21 of the example of FIG. 10.

On the other hand, assuming s=0 in the s-initializing operation permitsthe following calculation.z=y1 OR /y2

FIGS. 11B and 11D are respectively the equivalent circuit and symbolicdiagram of the logical calculation circuit 21 with s=0 in thes-initializing operation. In this way, it is possible to performintended logical calculation utilizing the data write operation to theferroelectric capacitor Cs.

Incidentally in the calculation operation (Op.) as shown in FIG. 10,because the preset line PRE is given “1”, the potential of the outputline ML becomes “L” and “H” respectively corresponding to z=1 and z=0.Further, in operations other than the calculation operation (Op.),because the preset line PRE is given “0”, the potential of the outputline ML becomes “H” in level (in the state of the transistor MP beingoff).

Next, FIG. 12 is a timing chart for performing logical calculation usingthe data read operation of the logical calculation circuit 21. Referringto FIG. 12, operation of read logical calculation with the logicalcalculation circuit 21 is described. In the case of read logicalcalculation, as shown in FIG. 12, data write operation (WO) is followedby data read operation (RO).

First, in the data write operation (WO), the control lines WL and RL arerespectively given “1” and “0”. The bit line BLw is given y1=/y. The bitlines BL1 and BL2 are given y2=y.

With this operation, the residual polarized state s of the ferroelectriccapacitor Cs and the residual polarized state s′ of the ferroelectriccapacitor Cs′ are updated. In other words, with the write operation(WO), the following calculation is initiated and the result is stored.s=/sb AND /y1 AND y2 OR sb AND (/y1 OR y2)

Because the example of FIG. 12 is asssumed with y1=/y and y2=y, theabove equation is expressed as follows.s=y

In other words, with the data write operation (WO.), y is stored as thefirst data to be calculated s.

The subsequent data read operation (RO) is performed in the order of aninitialize operation (Init.) followed by a calculation operation (Op.).In the initialize operation (Init.), the control lines WL and RL arerespectively given “0” and “1”. The bit lines BL1 and BL2 are given thereference potential c.

The initializing operation allows the coupling node 11 to be pre-chargedto the reference potential c corresponding to a specified logicaloperator without changing the residual polarized states s and s′ of theferroelectric capacitor Cs and the ferroelectric capacitor Cs′.

In the calculation operation (Op.) performed after the initializeoperation (Init.), as shown in FIG. 12, the control lines WL and RL arerespectively given “0” and “0”. The bit lines BL1 and BL2 arerespectively given the second data to be calculated x and the referencepotential c. With this operation, the transistor MP turns on or offaccording to the potential generated at the coupling node 11.

With on and off states of the transistor MP made to correspond to z=1and z=0, they are expressed as follows.z=/c AND x AND /s OR c AND (x OR /s)

Putting the calculation contents of the data write operation (WO) intothe above equation, the example of FIG. 12 is to perform the followingcalculation.z=/c AND x AND /y OR c AND (x OR /y)

FIGS. 13A and 13C are respectively an equivalent circuit and a symboldiagram of the logical calculation circuit 21 assuming the referencepotential c=0 in the example of FIG. 12. FIGS. 13B and 13D arerespectively an equivalent circuit and a symbol diagram of the logicalcalculation circuit 21 assuming the reference potential c=1 in theexample of FIG. 12. In this way, it is possible to perform intendedlogical calculation utilizing the data read operation to theferroelectric capacitor Cs.

Incidentally in the calculation operation (Op.) as shown in FIG. 12,because the preset line PRE is given “1”, the potential of the outputline ML becomes “L” and “H” respectively corresponding to z=1 and z=0.Further, in operations other than the calculation operation (Op.),because the preset line PRE is given “0”, the potential of the outputline ML becomes “H” in level (in the state of the transistor MP beingoff).

Also FIG. 14 is another timing chart for performing logical calculationusing the data read operation of the logical calculation circuit 21.While this is the same as the example of FIG. 12 regarding theperforming of the read logical calculation by using the logicalcalculation circuit 21, the example of FIG. 14 is different in that arestoration operation (Res.) is performed at the end of the data readoperation (RO).

As shown in FIG. 14, in the restoration operation (Res.) ensuing on thecalculation operation (Op.), the control lines WL and RL arerespectively given “0” and “0” in the same manner as the calculationoperation. On the other hand, the bit lines BL1 and BL2 are respectivelygiven the reference potential c and the second data to be calculated x,contrary to the calculation operation.

FIGS. 15A, 15B, and 15C respectively show the polarized states of theferroelectric capacitor Cs and the ferroelectric capacitor Cs′ of theexample shown in FIG. 14 respectively in initialize operation (Init.),calculating operation (Op.), and restoring operation (Res.).

Referring to FIGS. 15A, 15B, and 15C, and taking note of theferroelectric capacitor Cs, its polarized state is described. Theferroelectric capacitor Cs in the (residual) polarized state P2 with theinitialize operation (Init.) shown in FIG. 15A is changed to thepolarized state P5 by the calculation operation (Op.) shown in FIG. 15B.

Although polarity of the ferroelectric capacitor Cs is not reversed inthe state indicated with P5, it is displaced to some extent from theoriginal residual polarized state indicated with P2. Therefore, if thisstate is left as it is or the same data read operation is repeated, thehysteresis characteristic of the ferroelectric capacitor Cs might changeand correct data reading might be hindered.

Therefore, in the example of FIG. 14, the restoration operation (Res.)shown in FIG. 15C is performed to forcibly change the polarized state ofthe ferroelectric capacitor Cs to the state indicated with P6. With thisoperation, it is possible to correct the displacement of the polarizedstate of the ferroelectric capacitor Cs caused by the calculationoperation (Op.).

Next, FIG. 16A is a diagram of a logical calculation circuit 31according to still another embodiment of the invention. The logicalcalculation circuit 31 is of the same constitution as that of thelogical calculation circuit 1 shown in FIG. 1.

However, in the data write operation (WO) using the logical calculationcircuit 31, as the third data to be calculated y1, /y is given to thebit line BLw, and as the fourth data to be calculated y2, y is given tothe bit lines BL1 and BL2. Therefore, the logical calculation circuit 31is expressed with symbols as shown in FIG. 16B.

FIG. 17 is an example timing chart of the operation of the logicalcalculation circuit 31. This timing chart is based on the timing chartof the operation of the logical calculation circuit 1 (See FIG. 2),assuming that the third data to be calculated y1=/y and the fourth datato be calculated y2=y.

Therefore, also in the example of FIG. 17, assuming that on and offstates of the transistor MP correspond to z=1 and z=0, they areexpressed as follows, like in the examples shown in FIGS. 12 and 14.z=/c AND x AND /y OR c AND (x OR /y)

Therefore, as shown in FIG. 17, with the reference potential c=0 andc=1, the same logical calculation circuit 31 permits the following twokinds of logical calculations.z=x AND /y and z=x OR /y

Incidentally, FIGS. 18A, 18B, 18C, 19A, and 19B are circuit diagrams forexplaining, respectively, the data write operation (WO), theinitializing operation in the data read operation (RO, Init.), thecalculation operation in the data read operation (RO, Op.), therestoration operation in the data read operation (RO, Res.) and standbystate (Standby) of the logical calculation circuit 31.

These circuit diagram for explaining respective operations are based onthe circuit diagrams (FIGS. 3A, 5A-5C, and 3B) for explaining respectiveoperations of the logical calculation circuit 1, assuming that the thirddata to be calculated y1=/y and the fourth data to be calculated y2=y.Therefore, their explanations are not repeated here.

A plural number of the above-described, various kings of logicalcalculation circuits may be arranged in series and/or parallel torealize a logical calculation device to permit intended logicalcalculations.

FIG. 20 is a block diagram of a content addressable memory 41, which isa logical calculation device utilizing the logical calculation circuit31. The content addressable memory 41 is made to serve as a coincidencesearch device including a search word holding section 43, a word circuitarray section 45, a write drive section 47, and an output circuitsection 49.

The search word holding section 43 holds a search word X, an object ofsearch. The word circuit array section 45 is made up of a plural numberof word circuits 46, . . . . The write drive section 47 performs theoperation of writing a plural number of reference words Bi into the wordcircuit array section 45. The output circuit section 49 performsspecified processes according to the output of the word circuit arraysection 45.

FIG. 21 is a circuit diagram of the word circuit 46 constituted usinglogical calculation circuits 53, 55, . . . similar to the logicalcalculation circuit 31. FIG. 22A is a circuit diagram of a CAM cell(content addressable memory cell) 51 made up of a pair of logicalcalculation circuits 53 and 55 as components. One CAM cell 51 performsone-bit coincidence judgment process.

FIG. 23 is a timing chart showing the operation of the CAM cell 51. TheCAM cell 51 performs a data write operation (WO) followed by a data readoperation (RO). In FIG. 23, the first column (leftmost) indicates thedata write operation (WO) to the CAM cell 51. The second (from the left)column shows that the data to be written to the CAM cell of the samecolumn constituting the word circuit of the next line are transmittedthrough bit lines BLj1 a, BLj1 b, BLj2 a, and BLj2 b.

The bit lines BLj2 a, BLj2 b, and BLj1 b, of the logical calculationcircuit 53 constituting the CAM cell 51 shown in FIG. 22A correspond tothe bit lines BL1, BL2, and BLw of the logical calculation circuit 31shown in FIG. 16. Further, bit lines BLj1 a, BLj1 b, and BLj2 a in thelogical calculation circuit 55 constituting the CAM cell 51 correspondto the bit lines BL1, BL2, and BLw in the logical calculation circuit31.

Therefore, comparing the timing chart of FIG. 23 with that of FIG. 17,it is understood that the logical calculation circuits 53 and 55 of theCAM cell 51 respectively perform the following logical calculations.zi31u=x31 OR bi31 and zi31d=/x31 OR /bi31

FIG. 22B shows the CAM cell 51 expressed as a logical circuit. When theleft equation, zi31 u, of the two equations above becomes “1”, thetransistor 54 of the logical calculation circuits 53 turns on. When theright equation, zi31 d, of the two equations above becomes “1”, thetransistor 56 of the logical calculation circuits 55 turns on.

Therefore, in the case x31 and bi31 are different, both the transistors54 and 56 turn on. In the case x31 and bi31 are the same, one of thetransistors 54 and 56 turns off. Further, the transistors 54 and 56 areconnected in series.

Therefore, it is understood by referring to FIG. 21 that the outputpotential of the CAM cell 51 is “0” when x31 is different from bi31, andis “1” when x31 is equal to bi31. In other words, the CAM cell 51 may beseen as a circuit for calculating x31 EXNOR bi31 (negation of exclusiveOR of x31 and bi31).

As shown in FIG. 21, other CAM cells constituting the word circuit 46are also of the same constitution as that of the CAM cell 51 and theiroutputs are all connected in parallel.

Therefore, with the word circuit 46, Zi(X, Bi)=0 only when the 32-bitsearch word X and the reference word Bi are in complete coincidence,otherwise Zi(X, Bi)=1. In other words, the work circuit 46 calculatesZi(X, Bi) according to the equation given below.Zi(X, Bi)=0 (X=Bi) or 1 (X≠Bi)

A coincidence search device having functions of both memory andcalculation may be realized as described above using the logicalcalculation circuit 31 shown in FIG. 16.

Next, FIG. 24 is a block diagram of a content addressable memory 61 as alogical calculation device utilizing the logical calculation circuit 31above. The content addressable memory 61 is constituted as a device forcomparing magnitudes, and includes a search word holding section 63, aword circuit array section 65, a write drive section 67, and an outputcircuit section 69.

The search word holding section 63 holds the search word X to besearched. The word circuit array section 65 is made up of a pluralnumber of word circuits 66, . . . . The write drive section 67 performsthe operation of writing a plural number of reference words Bi into theword circuit array section 65. The output circuit section 69 performsspecified processes according to the output of the word circuit arraysection 65.

FIG. 25 is a diagram of the word circuit 66 constituted using logicalcalculation circuits 73, 75, . . . similar to the logical calculationcircuit 31. FIG. 26A is a circuit diagram of a CAM cell (ContentAddressable Memory Cell) 71 made up of components, a pair of logicalcalculation circuits 73 and 75.

FIG. 27 is a timing chart of the operation of the CAM cell 71. In theCAM cell 71, the data write operation (WO) is followed by the data readoperation (RO). In FIG. 27, the first column (leftmost) indicates thedata write operation (WO) to the CAM cell 71. The second (from the left)column shows that the data to be written to the CAM cell of the samecolumn constituting the word circuit of the next line are transmittedthrough bit lines BLjc0 a, BLjc0 b, BLjc1 a, BLjc1 b and BLjw.

The bit lines BLjc0 a, BLjc0 b, and BLjw, of the logical calculationcircuit 73 constituting the CAM cell 71 of FIG. 26A correspond to thebit lines BL1, BL2, and BLw of the logical calculation circuit 31 shownin FIG. 16. Further, bit lines BLjc1 a, BLjc1 b, and BLjw in the logicalcalculation circuit 55 of the CAM ell 51 correspond to the bit linesBL1, BL2, and BLw in the logical calculation circuit 31.

Therefore, by comparing the timing chart of FIG. 27 with that of FIG.17, it is understood that the logical calculation circuits 73 and 75 ofthe CAM cell 71 respectively perform the following logical calculations.zi31u=x31 AND /bi31 and zi31d=x31 OR /bi31

FIG. 26B shows the CAM cell 71 expressed as a logical circuit. When theleft equation, zi31 u, of the two equations above becomes “1”, thetransistor 74 of the logical calculation circuits 73 turns on. When theright equation, zi31 d, of the two equations above becomes “1”, thetransistor 76 of the logical calculation circuits 75 turns on.

On the other hand, x31 AND /bi31=1 means x31>bi31; and x31 AND /bi31=0means x31<=bi31. Further, x31 OR /bi31=1 means x31>=bi31; and x31 OR/bi31=0 means x31<bi31.

Therefore, if x31>bi31, the transistor 74 turns on; if x31<=bi31, thetransistor 74 turns off. Further, if x31>=bi31, the transistor 76 turnson; if x31<bi31, the transistor 76 turns off.

As shown in FIG. 25, other CAM cells, excluding that in the lowermostposition (rightmost in the figure) constituting the word circuit 66, arethe same in constitution as the CAM cell 71. The lowermost CAM cell ismade of only a logical calculation circuit, a counterpart of the logicalcalculation circuit 73 of the CAM cell 71.

Therefore, referring to FIG. 25, it is understood that the word circuit66 is constituted to produce a comparison decision output to the effectthat the search word X is greater than the reference word Bi in the casethe value of at least one bit xm in question out of respective bits xjconstituting the search word X is greater than the value of acounterpart bit bim of the reference word Bi, and the values ofrespective bits xk higher in position than the bit xm in question out ofthe respective bits xj constituting the search word X are respectivelyequal to the values of respective counterpart bits bik of the referenceword Bi.

In other words, the word circuit 66 compares the magnitudes of thesearch word X and the reference word Bi, both having the same 32 bits.This results in Zi(X, Bi)=1 only when the search word X is greater thanthe reference word Bi, otherwise results in Zi(X, Bi)=0. In other words,it is understood that the word circuit 66 calculates Zi(X, Bi) accordingto the equations given below.Zi(X, Bi)=1 (X>Bi) or 0 (X<=Bi),

where Zi(X, Bi)=gn−1 OR gen−1 AND (gn−2 OR gen−2 AND (gn−3 OR . . . ge2AND (g1 OR ge1 AND g0)) . . . )

In other words, Zi(X, Bi)=gn−1 OR gen−1 AND gn−2 OR gen−1 AND gen−2 ANDgn−3 OR . . . ge2 AND ge1 AND g0,

where gj=xj AND /bij and gej=xj OR /bij.

In this way, a magnitude comparison device having functions of bothmemory and calculation may be realized by the use of the logicalcalculation circuit 31 shown in FIG. 16.

Next, FIG. 28A shows a logical calculation circuit 81 in still anotherembodiment of the invention. The logical calculation circuit 81 is anexample of logical calculation circuit for use in the logicalcalculation device that performs pipelined process.

The logical calculation circuit 81 is similar to the logical calculationcircuit 21 shown in FIG. 9 in that it includes: a storage ferroelectriccapacitor Cs and a load ferroelectric capacitor Cs′ connected at thecoupling node 11, a transistor MP with its gate terminal connected tothe coupling node 11, and transistors Mw, M3, and M4.

However, it is different from the logical calculation circuit 21 in thatit includes transistors M5, M6, M7, and M8 in place of the transistorsM1 and M2, and further an inverter 83.

In other words, the logical calculation circuit 81 is constituted sothat the second terminal 5 of the ferroelectric capacitor Cs is given“1” through the transistor M7, and the fourth terminal 9 of theferroelectric capacitor Cs′ is given “0” through the transistor M8. Thegate terminals of the transistors M7 and M8 are connected respectivelyclock lines CLK1 and CLK2.

It is constituted that the coupling node 11 is given the third data tobe calculated y1 through the transistor Mw, and the fourth terminal 9 ofthe ferroelectric capacitor Cs′ is given the fourth data to becalculated y2 through the transistor M6. It is also constituted that thefourth terminal 9 of the ferroelectric capacitor Cs′ and the secondterminal 5 of the ferroelectric capacitor Cs are interconnected throughthe transistor M5.

Therefore, the second terminal 5 of the ferroelectric capacitor Cs isgiven the fourth data to be calculated y2 through the transistors M5 andM6. The gate terminals of the transistors Mw and M5 are both connectedto the clock line /CLK2. The gate terminal of the transistor M6 isconnected to the clock line /CLK1.

The gate terminals of the transistors M3 and M4 are both connected tothe clock line CLK2. The output signal from the transistor MP is takenout through the output line ML and the inverter 83. FIG. 28B is a symboldiagram of the logical calculation circuit 81.

Next, the operations of the logical calculation circuit 81 aredescribed. FIG. 29 is an example timing chart of the operation of thelogical calculation circuit 81. FIGS. 30A and 30B are respectivelycircuit diagrams for explaining the reset operation (Reset) and datawrite operation (WO) of the logical calculation circuit 81. FIGS. 31Aand 31B are respectively circuit diagrams for explaining the data readoperation (RO) of the logical calculation circuit 81.

As shown in FIG. 29, the logical calculation circuit 81 performs onecycle of operations in the order of reset operation (Reset), data writeoperation (WO), and data read operation (RO).

In the reset operation (Reset), the clock lines CLK1, /CLK1, CLK2, and/CLK2 are respectively given “1”, “0”, “0”, and “1”. Further, y1 isequal to 0. Therefore, as shown in FIG. 30A, the reset operation (Reset)makes the residual polarized states of the ferroelectric capacitor Csand the ferroelectric capacitor Cs′ respectively s=1 and s′=0.

As shown in FIG. 29, in the ensuing data write operation (WO), the clocklines CLK1, /CLK1, CLK2, and /CLK2 are respectively given “0”, “1”, “0”,and “1”.

Therefore, as shown in FIG. 30B, the residual polarized state s of theferroelectric capacitor Cs and the residual polarized state s′ of theferroelectric capacitor Cs′ are updated. That is, the data writeoperation (WO) makes the following calculation and the results arestored.s=/sb AND /y1 AND y2 OR sb AND (/y1 OR y2)

In this example, because sb=1 by the reset operation (Reset), the aboveexpression becomes as follows.s=/y1 OR y2=/(y1 AND /y2)

Here, a new polarized state s′ of the ferroelectric capacitor Cs′ isexpressed with the following equation.s′=y1 AND /y2

As shown in FIG. 29, the ensuing data read operation (RO) is performedin the order of initialize operation (Init.) and calculation operation(Op.). In the initialize operation (Init.), the clock lines CLK1, /CLK1,CLK2, and /CLK2 are respectively given “0”, “1”, “0”, and “1”. Further,it is made that y1=0 and y2=0.

As shown in FIG. 31A, the above operations allows the coupling node 11to be pre-charged with the reference potential c corresponding to aspecified logical operator without changing the residual polarizedstates s and s′ of the ferroelectric capacitors Cs and Cs′. In thisexample, the reference potential c=0.

In the calculation operation (Op.) subsequent to the initializeoperation (Init.), the clock lines CLK1, /CLK1, CLK2, and /CLK2 arerespectively given “1”, “0”, “1”, and “0”.

As shown in FIG. 31B, the second terminal 5 of the ferroelectriccapacitor Cs and the fourth terminal 9 of the ferroelectric capacitorCs′ are respectively given “1” and “0”. That is, the second data to becalculated x and the reference potential c corresponding to a specifiedlogical operator are respectively x=1 and c=0. This operation causes thetransistor MP to turn on or off according to the potential occurring atthe coupling node 11.

With the on and off states of the transistor MP made to correspond toz=1 and z=0, they are expressed with the equation below.z=/c AND x AND /s OR c AND (x OR /s)

In this example, because x=1 and c=0, the above equation is expressed asz=/s.

Putting the calculation contents of the above data write operation (WO)into the above equation results in that the logical calculation circuit81 of FIG. 28 performs the following calculation.z=//(y1 AND /y2)=y1 AND /y2

Further, if it is made that s=0 in the above reset process (Reset), itia possible to perform the following calculation.z=y1 OR /y2

FIG. 32 is an example block diagram of a pipelined logical calculationdevice 91 using a plural number of logical calculation circuits. Thepipelined logical calculation device 91 of FIG. 32 is a device forperforming a pipelined process in which a series of logical calculationsare divided into a plural number of stages to be implementedsequentially.

This example is constituted to perform logical calculations in threestages. To perform calculations in the first stage (Stage 1), the secondstage (Stage 2), and the third stage (Stage 3), the first stagecalculation section 93, the second stage calculation section 95, and thethird stage calculation section 97 are connected in series.

In this example, the respective calculation sections 93, 95, and 97 areconstituted as a functional pass-gate network (FPGN) using a pluralnumber of the above logical calculation circuits 81.

It is constituted that the first and third stage calculation sections 93and 97 operate according to signals of the clock lines CLK1 and CLK2,and the second stage calculation section 95 operates according to thesignals of the clock lines CLK1 and CLK3.

FIG. 33 is an example timing flowchart of the operation of the pipelinedlogical calculation device 91. As shown in FIG. 33, the signal of theclock line CLK3 is delayed by a half cycle from the signal of the clockline CLK2. Therefore, calculation operations go on sequentially with ahalf-cycle delay one after another in the order of the first stage(Stage 1), second stage (Stage 2), and the third stage (Stage 3).

As described above, when the pipelined process is performed, forexample, using a plural number of the logical calculation circuits 81,storage and calculation indispensable for the pipelined process need notbe performed with different circuits, so that the space required forwiring is reduced by a great margin.

FIG. 34 is a block diagram of constitution of the pipelined logicalcalculation device of FIG. 32 embodied as a full adder 101. The fulladder 101 shown in FIG. 34 is a pipelined signed-digit full adder forperforming addition of signed-digit binary numbers by pipelines process.

The full adder 101 divides addition of signed-digit binary numbers intofour states and sequentially performs calculation stages. To performcalculations in the first stage, the second stage, the third stage, andthe fourth stage, the first stage calculation section 101 a, the secondstage calculation section 101 b, the third stage calculation section 101c, and the fourth stage calculation section 101 d are connected inseries.

In this example, the first to fourth stage calculation sections 101a-101 d are each embodied as a functional pass-gate network (FPGN)respectively using the above logical calculation circuit 81 as afunctional pass-gate (FP).

It is constituted that both the first and third stage calculationsections 101 a and 101 c operate according to the signals of the clocklines CLK1 and CLK2, and both the second and fourth stage calculationsections 101 b and 101 d operate according to the signals of the clocklines CLK1 and CLK3.

Therefore, with the full adder of FIG. 34, operations of addition go onin the order of the first, second, third, and fourth stages with ahalf-cycle delay one after another. FIG. 35 is an equivalent circuitdiagram of the full adder 101 expressed with logical circuits.

As is seen from FIGS. 34 and 35, the first stage calculation section 101a of the full adder 101, using two logical calculation circuits 81,calculates two binary numbers (ai⁺ OR ai⁻) and (bi⁺ OR bi⁻)corresponding to signed-digit binary numbers, an augend (ai⁺, ai⁻) andan addend (bi⁺, bi⁻).

The first stage calculation section 101 a, using other two logicalcalculation circuits 81, and based on the augend (ai⁺, ai⁻) and theaddend (bi⁺, bi⁻), calculates ki=ai⁺ OR bi⁺ and a first carryinformation hi=ai⁻ OR bi⁻ of the bit in question, and stores them.

The second stage calculation section 101 b, using a pair of logicalcalculation circuits 81 connected in parallel, calculates one binarynumber 1i=(ai⁺ OR ai⁻) EXOR (bi⁺ OR bi⁻) corresponding to the exclusiveOR of two binary numbers (ai⁺ OR ai⁻) and (bi⁺ OR bi⁻) stored in theprevious stage, as a first addition result and stores it.

The second stage calculation section 101 b takes in ki and the firstcarry information hi both stored in the previous stage and stores themusing two logical calculation circuits 81.

The third stage calculation section 101 c, using another pair of thelogical calculation circuits 81 connected in parallel, calculates onebinary number αi=1i EXOR hi−1 corresponding to the exclusive OR of thefirst addition result 1i stored in the previous stage and the firstcarry information hi−1=ai−1⁻ OR bi−1⁻ from the previous bit as thesecond addition result and stores it.

Also the third stage calculation section 101 c, based on the ki, thefirst addition result li, both stored in the previous stage, and thefirst carry information hi−1 from the previous bit, and using twological calculation circuits 81, calculates the second carry informationin the bit in question βi=/li AND ki OR li AND /hi−1, and stores it.

The fourth stage calculation section 101 d, based on the second additionresult αi stored in the previous stage, and the second carry informationβi−1=/li−1 AND ki−1 OR li−1 AND /hi−2 from the previous bit, and usingtwo logical calculation circuits 81, calculates a signed-digit binarynumber (si⁺, si⁻) as an addition result of the logical calculationdevice 101 according to the equation given below.si ⁺ =/αi AND βi−1 and si ⁻ =αi AND /βi−1

Here, the signed-digit binary number (ai⁺, ai⁻) is assumed to take oneof values (1, 0), (0, 0), and (0, 1), and respectively corresponds to 1,0, and −1. In other words, it may be defined that the signed-digitbinary number (ai⁺, ai⁻)=ai⁺−ai⁻. This is also true for othersigned-digit binary numbers.

Approximately the right half of the logical calculation circuit 101shown in FIG. 35 corresponds to the addition result calculation section,and approximately the left half to the carry information calculationsection.

FIG. 36 is an example block diagram of a pipelined multiplier using aplural number of the full adder 101 of FIG. 34 as element calculationdevices. The pipelined multiplier 111 shown in FIG. 36 is a device forperforming pipelined multiplication process in which multiplication isdivided into a plural number of levels to be sequentially processed. Inthis example, the multiplier 111 is assumed to be constituted to performmultiplication of binary numbers of 54×54 bits.

The multiplier 111 includes a partial product generating section 112 andan addition section 117. The partial product generating section 112includes a booth encoder 113 and a partial product generator 115 togenerate a partial product corresponding to a multiplicand and amultiplier.

That is, the partial product generating section 112 first uses asecond-order Booth's algorithm to produce, from a 54-bit multiplicand xand a 54-bit multiplier y, 27 pieces of partial products correspondingto approximately half the number of bits of the multiplier y.Approximately half of these partial products, or 13 partial productscorresponding to even number-th partial products, are inverted partialproducts (with all the component bits inverted). The inverted partialproducts are named as /PP2, /PP4, . . . , /PP26 and non-inverted partialproducts as PP1, PP3, . . . , PP27.

Next, the partial product generating section 112 produces onesigned-digit partial product for a pair of adjacent partial products. Inother words, signed-digit partial products SDPP1, SDPP2, . . . , SDPP13are produced respectively from partial products PP1 and /PP2, PP3 and/PP4, . . . , PP25 and /PP26.

It is constituted for example on the assumption that the i-th bits ofthe partial products PP3 and /PP4 are respectively ppi3 and /ppi4, thesigned-digit partial product SDPP2 with the i-th bit being asigned-digit binary number (ppi3, /ppi4) is produced. According to theabove definition of the signed-digit binary number (ai⁺, ai⁻)=ai⁺−ai⁻,(ppi3, /ppi4)=ppi3−/ppi4. It is assumed to express the aboverelationship of the partial products PP3, /PP4, and the signed-digitpartial product SDPP2 as SDPP2=(PP3, /PP4)=PP3−/PP4.

Because an expression using a complement of 2 results inPP3+PP4=PP3−/PP4−1, it becomes PP3+PP4=SDPP2−1=SDPP2+(0, 1). In otherwords, the sum of a pair of PP3 and PP4 may be expressed as asigned-digit binary number obtained by adding an additional binarysigned-digit binary number (0, 1) to the lowermost bit of one signedSDPP2.

Likewise, the sum of the other pair of partial products PP5 and PP6 maybe expressed as a signed-digit binary number obtained by adding anadditional binary signed-digit binary number (0, 1) to the lowermost bitof one signed SDPP3. In other words, PP5+PP6=SDPP3+(0, 1). Other pairsof partial products are similar to the above.

Further, as for the last partial product PP27, only itself is used toproduce a signed-digit partial product SDPP14. Furthermore, asigned-digit partial product SDPP15, with component element of asigned-digit binary number (0, 1) to be added to the lowermost bit ofrespective signed-digit partial products SDPP1 through SDPP14, isproduced. In this way, 15 pieces, approximately one fourth of the bitnumber of the multiplier y, of signed-digit partial products SDPP1through SDPP15 are produced.

An addition section 17 includes a first level calculation section 117 a,a second level calculation section 117 b, a third level calculationsection 117 c, and a fourth level calculation section 117 d respectivelyfor performing addition of the first, second, third, and fourth levels.The addition section 117 performs sequentially addition of respectivelevels using the Wallace-tree method and based on the signed-digitpartial products SDPP1 through SDPP15 produced with the partial productgenerating section 112 to obtain results.

The respective level calculation sections 117 a-117 d each includes oneor more addition units 119 (signed-digit adders: SDA). FIG. 37 is ablock diagram of constitution of an adder unit 119. Each addition unit119 is made by parallel connection of full adders 101 in a numbercorresponding to the bit number of the signed-digit partial productproduced with the partial product generating section 112 to outputaddition results, signed-digit binary numbers in a number correspondingto the relevant bit number. In this embodiment, the bit number of theaddition unit 119 is made to be approximately the same as that of theproduct of the multiplicand x and the multiplier y.

The first level calculation section 117 a, using seven pieces ofaddition units 119 connected in parallel, performs additions in paralleloperation using inputs of the signed-digit partial products SDPP15, andSDPP1 through SDPP13 to obtain the first level addition results, sevenin number that is substantially half the number of the signed-digitpartial products produced in the partial product generating section 112,and stores the results.

In the example of FIG. 36, the addition unit 119 in the leftmostposition of the first level calculation section 117 a adds together thesigned-digit partial products SDPP15 and SDPP1, the addition unit 119second from the left adds together the signed-digit partial productsSDPP2 and SDPP3, and the rightmost addition unit (not shown) addstogether the signed-digit partial products SDPP12 and SDPP13.

For example, the addition unit 119, second from the left of the firstlevel calculation section 117 a, adds together the signed-digit partialproducts SDPP2 and SDPP3. Therefore, the above-mentioned (ppi3, /ppi4)or the respective bit values of the signed-digit partial product SDPP2are inputted as the respective bit values ai=(ai⁺, ai⁻) of the augend“a” as shown in FIG. 37. The above-mentioned (ppi5, /ppi6) or therespective bit values of the signed-digit partial product SDPP3 areinputted as the respective bit values bi=(bi⁺, bi⁻) of the addend “b” asshown in FIG. 37.

The second level calculation section 117 b, using the four additionunits 119 arranged in parallel, and using the addition results of theprevious level as inputs, calculates the second level addition resultsin a number that is substantially half that of the previous level, andstores the results.

In the example of FIG. 36, the addition unit 119 in the leftmostposition of the second level calculation section 117 b adds together twofirst level addition results calculated with the leftmost-locatedaddition unit 119 and the addition unit 119 located second from the leftof the first level calculation section 117 a to obtain one second leveladdition result. The addition units 119 located second and third (notshown) from the left of the second level calculation section 117 bperform similar calculations.

Further, the rightmost-located addition unit 119 (not shown) of thesecond level calculation section 117 b adds together the signed-digitpartial product SDPP14 and one first level addition result obtained withthe rightmost-located addition unit 119 (not shown) of the first levelcalculation section 117 a. In this way, four pieces of the second leveladdition results are obtained.

The third level calculation section 117 c, using two addition units 119located in parallel and using the four addition results calculated inthe previous level as inputs, performs addition to obtain third leveladdition results, two in number that substantially corresponds to halfthe number in the previous level, and stores the results.

The fourth, last level calculation section 117 d, using one additionunit 119 and the two addition results calculated in the previous levelas inputs, performs addition to obtain the one, last level additionresult, and stores the calculated last level addition result as asigned-digit binary number corresponding to the product of theabove-described multiplicand and multiplier.

As described above, in the pipelined multiplier 111, the partial productgenerating section 112, using the second-order Booth's algorithm,produces 27 pieces of partial products PP1-PP27 for the multiplicand xand the multiplier y. At the same time, based on the 27 partial productsproduced, the partial product generating section 112 produces 15 piecesof signed-digit partial products SDPP1 through SDPP15. The additionsection 117 of the pipelined multiplier 111, using the Wallace-treemethod, produces a signed-digit binary number corresponding to theproduct of the multiplicand x and the multiplier y by adding up the 15pieces of signed-digit partial products SDPP1-SDPP15. After that,specified conversion is made to obtain a product of the multiplicand xand the multiplier y.

FIG. 38 is an example constitution of a pipelined multiplier ofseries-parallel type using the logical calculation circuit 81 shown inFIG. 28A. The pipelined multiplier 141 is constituted to performmultiplication of a four-bit multiplicand s and a four-bit multiplier bin a number of levels in succession, with the number being four, thenumber of bits of the multiplier b. As shown in FIG. 38, the firstthrough fourth level calculation sections 141 a-141 d performcalculations of the first through fourth levels.

For example, the second level calculation section 141 b includes anelementary partial product generating section or a logical productcircuit 142, and an elementary calculation device or a pipelined fulladder 143 of series type. In the figure, the symbol st in a squaredenotes a memory section, and the symbol + in a circle denotes a fulladder. The second and third level calculation sections 141 c and 141 dare of similar constitution, except that the first level calculationsection 141 a does not include the full adder.

FIG. 39 is an explanatory diagram of the operation of the pipelinedmultiplier 141. The figure shows sequential operations of the first tofourth levels from left to right. The operations in each level are shownto proceed from top to bottom (with the lapse of time). In the figure,the encircled letter V is a symbol showing the logical product circuit142. In the second through fourth levels in the figure, the broken linewith arrow connecting adjacent full adders in the same level indicatesthe flow of carry.

For example, the operation in the second level calculation section 141 bof the pipelined multiplier 141, or the second level operation, isindicated with the column second from the left in FIG. 39. Therefore,the operation of for example the third step (third cycle) of the secondlevel calculation section 141 b is indicated with the operation locatedsecond from left and third from top in FIG. 39, indicated with Q. Theoperation in the third step of the second level calculation section 141b of the pipelined multiplier 141 is described below.

First, the logical product circuit 142 calculates a logical product of amultiplicand bit s1 to be currently calculated in the second level outof four bits constituting the multiplicand s, that is, a calculationobject bit s1 of the multiplicand s, and a bit b1 corresponding to thesecond level out of four bits constituting the multiplier b. Next, usingthe pipelined full adder 143, a sum is calculated for three binarynumbers: the above calculated logical product; the partial product inthe previous, first level; and the carry in the second level for the bits0 preceding the calculation object bit s1 of the multiplicand.

The result obtained with the pipelined full adder 143 is sent as apartial product in the second level of the calculation object bit s1 ofthe multiplicand to the next, third level. The carry produced by thisaddition is stored as the carry in the second level of the calculationobject bit s1 of the multiplicand.

The operations in the third and fourth level calculation sections 141 cand 141 d are the same as the above. However, the first levelcalculation section 141 a calculates a logical product or an elementaryproduct but does not perform addition.

FIG. 40 is a block diagram of constitution of the second levelcalculation section 141 b of the pipelined multiplier 141. FIG. 41 showsa logical circuit constitution of the second level calculation section141 b. A large number of oblong rectangles in FIG. 41 are respectivelymemories. The second level calculation section 141 b is constituted toperform logical calculation of the second level in four divided stagesin succession.

As shown in FIG. 40, the first to fourth stage calculation sections 145a-145 d of the second level calculation section 141 b performcalculations in the first to fourth stages. In the figure, each symbolFP in a squares denotes a logical calculation circuit (or functionalpass gate) 81 shown in FIG. 28A.

The first stage calculation section 145 a takes in one bit as an objectof calculation out of bits constituting the multiplicand s and stores itas a calculation object bit sj of the multiplicand.

The second stage calculation section 145 b, using the logical productcircuit 142, calculates the logical product, of the calculation objectbit sj of the multiplicand stored in the previous stage and the bit b1corresponding to the second level out of the bits constituting themultiplier b, as an elementary product in the second level of thecalculation object bit sj of the multiplicand, and stores the result.Further, the second stage calculation section 145 b takes in thecalculation object bit sj of the multiplicand stored in the first stage.

The third and fourth stage calculation sections 145 c and 145 d, usingthe pipelined full adder 143, calculate the sum of three binary numbers:the elementary partial product in the second level calculated in theprevious stage; the partial product Pj in the first level; and the carryC1 in the second level for the bit before the calculation object bit sjof the multiplicand, and stores the result as the partial product Pj+1in the second level of the calculation object bit sj of themultiplicand, and stores the carry produced by this addition as a newcarry in the second level for the calculation object bit sj of themultiplicand.

The third and fourth stage calculation sections 145 c and 145 d take inthe calculation object bit sj of the multiplicand, stored in the secondstage and stores it as the calculation object bit sj+1 of themultiplicand for the next, third level.

The third and fourth level calculation sections 141 c and 141 d are ofthe same constitution as the above second level calculation section b,except, as described above, the first level calculation section 141 adoes not include a logical calculation section for full addition.

Incidentally, the pipelined full adder 143 as shown in FIG. 40 may alsobe seen as a logical calculation device for performing first and secondaddition stages corresponding to the above third and fourth stages. Inthat case, the pipelined full adder 143 includes the first and secondaddition stage calculation sections for performing the first and secondstage calculations.

The first and second addition stage calculation sections constitutingthe pipelined full adder 143 is made by dropping the logical calculationcircuit 81 (functional pass gate) indicated at the right end in thefigure from both the third and fourth level calculation sections 145 cand 145 d shown in FIG. 40.

In other words, the first addition stage calculation section, using apair of the parallel-connected logical calculation circuits 81,calculates a binary number corresponding to the exclusive OR of thebinary numbers corresponding to the addend and augend as a firstaddition result, stores the result and stores the carry outputted in thesecond addition stage implemented immediately before.

The second addition stage calculation section, using another pair ofparallel-connected logical calculation circuit 81, calculates a binarynumber corresponding to the binary number corresponding to the exclusiveOR of the first addition result obtained in the first addition state andthe binary number corresponding to the carry stored in the firstaddition stage as a second addition result, stores the result, as wellas outputs the second addition result as a addition result of thepipelined full adder 143, calculates the carry in this addition using aplural number of the logical calculation circuits 81, and stores it.

Further, while the above embodiments are described assuming that thetransistors MP are N-channel MOSFETs, this invention is not limited bythe assumption. For example, this invention may also be embodied withthe transistors MP being P-channel MOSFETs.

Furthermore, while the above embodiments are described with an exampleof the calculation result output section being the field effecttransistor, the calculation result output section is not limited to it.In effect, the calculation result output section may be of any type aslong as it outputs the logical calculation result of the first andsecond data to be calculated according to the state change amounts ofboth non-volatile memory element and non-volatile load element obtainedby giving the second data to be calculated.

While the above embodiments are also described on the assumption thatferroelectric capacitors are used as the non-volatile memory element andnon-volatile load element, the non-volatile memory element and/ornon-volatile load element in this invention are not limited to theferroelectric capacitors. Generally, elements having hysteresischaracteristic may be taken into consideration as the non-volatileelements.

For example, elements using paraelectric capacitors may be used as thenon-volatile memory element and/or non-volatile load element, which willbe described later.

Further, the non-volatile memory element and/or non-volatile loadelement are not limited to those using capacitors. They can also useelements using resistances.

In the case elements using resistances are used as the non-volatilememory elements, both ends of the relevant resistance become the firstand second terminals. In the case elements using resistances are used asthe non-volatile load elements, both ends of the relevant resistancebecome the third and fourth terminals. In such cases, it is appropriatefor example to make resistance values different according to the firstdata to be calculated.

It is also possible to use elements using transistors as thenon-volatile memory element and/or non-volatile load element. In thecase for example an element using field effect transistors (FETs) isused as the non-volatile memory element, a pair of input and outputterminals (drain and source terminals) of the relevant FET become thefirst and second terminals.

In the case an element using FETs is used as the non-volatile loadelement, a pair of input and output terminals (drain and sourceterminals) of the relevant FET become the third and fourth terminals. Insuch cases, it is appropriate to constitute for example that anappropriate bias voltage according to the first data to be calculated isgiven to the gate terminal of the relevant FET.

It is further possible to use elements using the capacitors,resistances, and transistors in appropriate combination as thenon-volatile memory element and/or non-volatile load element.

FIG. 42A is an example circuit diagram of a non-volatile load elementutilizing paraelectric capacitor. The load element 121 shown in FIG. 42Ais used for example in the logical calculation circuit 31 shown in FIG.16 in place of the load ferroelectric capacitor Cs′, and includes twoparaelectric capacitors C1 and C2, a switch (transfer gate) 125, and amemory device 123.

The two paraelectric capacitors C1 and C2 are connected in parallelthrough the switch 125 to serve as a compound capacitor. One end of thecompound capacitor is connected through a coupling node 11 to the gateterminal of the transistor MP while the other end is connected to thebit line BL2. The memory device 123 stores data corresponding to thefirst data to be calculated s in non-volatile manner. The switch 125turns on and off according to the data stored in the memory device 123.

FIG. 43A shows an equivalent circuit of the load element 121 in the dataread operation (RO) when y=0 is given to the bit line BL2 in the datawrite operation (WO) of FIG. 17 (in other words when the first data tobe calculated s=0).

On the other hand, FIG. 43B shows an equivalent circuit of the loadelement 121 in the data read operation (RO) when y=1 is given to the bitline BL2 in the data write operation (WO) of FIG. 17 (in other wordswhen the first data to be calculated s=1).

It is understood from FIGS. 43A and 43B that the compound capacitance ofthe load element 121 at the time of the data read operation (RO) is C1or C1+C2, corresponding to the first data to be calculated s=0 or s=1.

FIG. 42B is a hysteresis diagram for explaining the data read operationof the logical calculation circuit 31 using a load element 121 as thenon-volatile load element. In this embodiment, the reference potentialis made c=0. It is understood from this figure that changing thecapacitance of the load element 121 according to the first data to becalculated s provides the same effect as that when the ferroelectriccapacitor Cs′ is used as the non-volatile load element.

FIG. 44A is another example circuit diagram of a non-volatile loadelement using a paraelectric capacitor. The load element 131 shown inFIG. 44A is used for example in the logical calculation circuit 31 shownin FIG. 16 in place of the ferroelectric capacitor Cs′ and includes aparaelectric capacitor C3, a memory device 133, and a load power source135.

One end of the paraelectric capacitor C3 is connected through thecoupling node 11 to the gate terminal of the transistor MP, while theother end is connected through the load power source 135 to the bit lineBL2. The memory device 133 stores data corresponding to the first datato be calculated s in non-volatile manner. The load power source 135 isa DC power source constituted to reverse in polarity according to thedata stored in the memory device 133.

FIG. 45A shows an equivalent circuit of the load element 131 in the dataread operation (RO) when y=0 is given to the bit line BL2 in the datawrite operation (WO) of FIG. 17 (in other words when the first data tobe calculated s=0). In this case, the polarity of the load power source135 is such that the other end of the paraelectric capacitor C3 ispositive relative to the bit line BL2.

On the other hand, FIG. 45B shows an equivalent circuit of the loadelement 131 in the data read operation (RO) when y=1 is given to the bitline BL2 in the data write operation (WO) of FIG. 17 (in other wordswhen the first data to be calculated s=1). In this case, the polarity ofthe load power source 135 is such that the other end of the paraelectriccapacitor C3 is negative relative to the bit line BL2.

It is understood from FIGS. 45A and 45B that the potential of the otherend of the paraelectric capacitor C3 of the load element 131 at the timeof the data read operation (RO) is +Vc or −Vc, corresponding to thefirst data to be calculated s=0 or s=1.

FIG. 44B is a hysteresis diagram for explaining data read operation ofthe logical calculation circuit 31 using a load element 131 as thenon-volatile load element. In this embodiment, the reference potentialis made c=0. It is understood from this figure that changing thepotential at the other end of the load element 131 (the end on the bitline BL2 side) according to the first data to be calculated s providesthe same effect as that when the ferroelectric capacitor Cs′ is used asthe non-volatile load element.

FIG. 46A is an example circuit diagram of a non-volatile memory elementusing paraelectric capacitors. The memory element 151 shown in FIG. 46Ais used for example in place of the storage ferroelectric capacitor Csin the logical calculation circuit 31 shown in FIG. 16, and includes twoparaelectric capacitors C1, C2, a switch (transfer gate) 155, and amemory device 153.

The two paraelectric capacitors C1 and C2 are interconnected parallelthrough the switch 155 to form a compound capacitor. One end of thecompound capacitor is connected to the bit line BL1 while its other endis connected through the coupling node 11 to the gate terminal of thetransistor MP. The memory device 153 stores data corresponding to thefirst data to be calculated s in non-volatile manner. The switch 155turns on and off according to the data stored in the memory device 153.

FIG. 47A shows an equivalent circuit of the memory element 151 in thedata read operation (RO) when y=0 is given to the bit line BL1 (in otherwords when the first data to be calculated s=0) in the data writeoperation (WO) of FIG. 17.

On the other hand, FIG. 47B shows an equivalent circuit of the memoryelement 151 in the data read operation (RO) when y=1 is given to the bitline BL1 (in other words when the first data to be calculated s=1) inthe data write operation (WO) of FIG. 17.

It is understood from FIGS. 47A and 47B that the compound capacitance ofthe memory element 151 at the time of the data read operation (RO) isC1+C2 or C1, corresponding to the first data to be calculated s=0 ors=1.

FIG. 46B is a diagram for explaining the data read operation of thelogical calculation circuit 31 using a memory element 151 as thenon-volatile memory element. In this embodiment, the reference potentialis made c=0. It is understood from this figure that changing thecapacitance of the memory element 151 according to the first data to becalculated s provides the same effect as that when the ferroelectriccapacitor Cs is used as the non-volatile memory element.

FIG. 48A is another example circuit diagram of a non-volatile memoryelement using paraelectric capacitors. The memory element 161 shown inFIG. 48A is used for example in place of the ferroelectric capacitor Csin the logical calculation circuit 31, and includes a paraelectriccapacitor C3, a memory device 163, and a storage power source 165.

One end of the paraelectric capacitor C3 is connected to the bit lineBL1 while its other end is connected through the storage power source165 and the coupling node 11 to the gate terminal of the transistor MP.The memory device 163 stores data corresponding to the first data to becalculated s in non-volatile manner. The storage power source 165 is aDC power source constituted to reverse in polarity according to the datastored in the memory device 163.

FIG. 49A shows an equivalent circuit of the memory element 161 in thedata read operation (RO) when y=0 is given to the bit line BL1 in thedata write operation (WO) of FIG. 17 (in other words when the first datato be calculated s=0). In this case, the polarity of the storage powersource 165 is such that the other end of the paraelectric capacitor C3is negative relative to the bit line BLw.

On the other hand, FIG. 49B shows an equivalent circuit of the memoryelement 161 in the data read operation (RO) when y=1 is given to the bitline BL1 (in other words when the first data to be calculated s=1) inthe data write operation (WO) of FIG. 17. In this case, the polarity ofthe storage power source 165 is such that the other end of theparaelectric capacitor C3 is positive in reference to the bit line BLw.

It is understood from FIGS. 49A and 49B that the potential of the otherend of the paraelectric capacitor C3 of the memory element 161 at thetime of the data read operation (RO) is −Vc or +Vc, corresponding to thefirst data to be calculated s=0 or s=1.

FIG. 48B is a diagram for explaining the data read operation of thelogical calculation circuit 31 using a memory element 161 as thenon-volatile memory element. In this embodiment, the reference potentialis made c=0. It is understood from this figure that changing thepotential at the other end of the memory element 161 (the end on the bitline BLw side) according to the first data to be calculated s providesthe same effect as that when the ferroelectric capacitor Cs is used asthe non-volatile memory element.

As described above, it is possible to use an element in which one of thenon-volatile load element and the non-volatile memory element is aferroelectric capacitor while the other is a paraelectric capacitor.

As a matter of course, it is also possible to use an element in whichboth of the non-volatile load element and the non-volatile memoryelement are paraelectric capacitors. For example, it is possible to useone of the above load elements 121 and 131 as the non-volatile loadelement, and use one of the memory elements 151 and 161 as thenon-volatile memory element.

Incidentally in this specification, the expression “A <=B” means that Ais smaller than or equal to B.

A logical calculation circuit of this invention is characterized bycomprising: a storage ferroelectric capacitor for retaining a polarizedstate corresponding to the first data to be calculated and having afirst and a second terminals; a load ferroelectric capacitor forretaining a polarized state corresponding to the first data to becalculated and substantially complementary to the polarized state of thestorage ferroelectric capacitor and having a third terminal connected tothe first terminal of the storage ferroelectric capacitor, and a fourthterminal; and a calculation result output section connected to acoupling node between the first terminal of the storage ferroelectriccapacitor and the third terminal of the load ferroelectric capacitor tooutput a logical calculation result of the first and second data to becalculated for a specified logical operator according to the potentialof the coupling node obtained by connecting the fourth terminal of theload ferroelectric capacitor to a specified reference potential and bygiving a second data to be calculated to the second terminal of thestorage ferroelectric capacitor.

In other words, the storage ferroelectric capacitor storing the firstdata to be calculated and the load ferroelectric capacitor storing adata of complementary relationship to the first data to be calculatedare interconnected in series at the coupling node to obtain a compoundferroelectric capacitor. When one end of the compound ferroelectriccapacitor is given a specified reference potential while its other endis given the second data to be calculated, a potential occurring at thecoupling node is read as the result of logical calculation on the firstand second data to be calculated for the specified logical operator.

Therefore, the operation of reading data from the compound ferroelectriccapacitor may be utilized to perform logical calculation. In otherwords, storage of data and logical calculation of data may be performedwith a single logical calculation circuit.

Constituting that the load ferroelectric capacitor is complementary inpolarity to the storage ferroelectric capacitor makes it possible toarrange that the coupling node potential at the time of reading data isgreatly different corresponding to the logical calculation result andthat the residual polarization of the storage ferroelectric capacitordoes not reverse by the data read operation. Therefore, it is possibleto realize a logical calculation circuit capable of performing logicalcalculations reliably at high speeds.

The logical calculation circuit of this invention is characterized inthat the specified reference potential is selectable from two or moredifferent reference potentials corresponding to two or more differentlogical operators, and that the specified logical operator is determinedby connecting the chosen reference potential to the fourth terminal ofthe load ferroelectric capacitor and by pre-charging the coupling nodewith the specified reference potential before giving the second data tobe calculated.

Therefore, it is possible to perform plural kinds of logicalcalculations using a single logical calculation circuit by a simpleoperation of choosing a specified reference potential in the data readoperation.

The logical calculation circuit is characterized in that the third datato be calculated is given to the coupling node and the fourth data to becalculated is given to both the second terminal of the storageferroelectric capacitor and the fourth terminal of the loadferroelectric capacitor, and that the polarized states of the storageferroelectric capacitor and the load ferroelectric capacitorcorresponding to the first data to be calculated are determined withboth the third and fourth data to be calculated given and the polarizedstates of the storage ferroelectric capacitor and the load ferroelectriccapacitor before the third and fourth data to be calculated are given.

In other words, the first data to be calculated, determined with the oldfirst data to be calculated present as stored in the compound capacitorbefore a data is written and the third and fourth data to be calculatedrespectively given to the coupling node and to both ends of the compoundcapacitor at the time of data writing, is written into the compoundcapacitor at the time of data writing.

Therefore, it is possible to perform logical calculations utilizing thedata write operation to the compound capacitor.

The logical calculation circuit of this invention is characterized inthat: a non-volatile memory element for retaining non-volatile statecorresponding to a binary data, a first data to be calculated s, andhaving first and second terminals; a non-volatile load element forretaining non-volatile state corresponding to /s, an inverted value ofthe first data to be calculated s, having a third terminal connected tothe first terminal of the non-volatile memory element, and a fourthterminal; and a calculation result output section for outputting alogical calculation result of the first and second data to be calculateds and x, as a calculation result data z as a binary data, for aspecified logical operator corresponding to a reference potentialaccording to the states of the non-volatile memory element and thenon-volatile load element obtained by pre-charging the coupling node ofthe first terminal of the non-volatile memory element and the thirdterminal of the non-volatile load element with the reference potentialand then giving the second data x as a binary data, to the secondterminal of the non-volatile memory element while maintaining the fourthterminal of the non-volatile load element at the reference potentialarbitrarily chosen out of two complementary reference potentials, inwhich the calculation result data z substantially meets the followingequation when the binary data corresponding to the two complementaryreference potentials are assumed to be c and /c,z=/c AND x AND /s OR c AND (x OR /s).

In other words, the non-volatile memory element having stored the firstdata s to be calculated and the non-volatile load element having storedthe reversal data /s of the first data s to be calculated are connectedin series at the coupling node to form a compound capacitor. Whilemaintaining one end of the compound capacitor at a reference potential cchosen arbitrarily from mutually complementary two reference potentials,the coupling node is pre-charged with the reference potential c. Then,when the second data x to be calculated is given to the other end, thestate of the compound capacitor is read as the calculation resultsubstantially meeting the equation given below.z=/c AND x AND /s OR c AND (x OR /s)

Therefore, it is possible to perform logical calculations utilizing theoperation of reading data from the compound non-volatile element. Inother words, storage and logical calculations of data may be performedwith a single logical calculation circuit.

Further, constituting that the non-volatile states of the non-volatileload element and the non-volatile memory element are complementary makesit possible that the state of the compound non-volatile element at thetime of reading data is greatly different corresponding to the logicalcalculation result. That is, data reading with great margin can beachieved. Therefore, it is possible to realize a logical calculationcircuit capable of performing logical calculations reliably at highspeeds.

It is further possible to perform plural kinds of logical calculationswith a single logical calculation circuit by a simple operation ofchoosing the specified reference potential c from two complementaryreference potentials in the data read operation.

The logical calculation circuit of this invention is characterized inthat the first data s to be calculated corresponds to a new non-volatilestate of the non-volatile memory element obtained by giving a binarydata, the third data y1 to be calculated, to the coupling node and bygiving a binary data, the fourth data y2 to be calculated, to both thesecond terminal of the non-volatile memory element and the fourthterminal of the non-volatile load element, and that when the first datato be calculated before the third and fourth data to be calculated aregiven is assumed to be sb, the following equation is satisfied.s=/sb AND /y1 AND y2 OR sb AND (/y1 OR y2)

In other words, the new first data s to be calculated determined withthe old first data sb to be calculated present in store in the compoundnon-volatile element before data is written and the third and fourthdata y1 and y2 to be calculated given to the coupling node and both endsof the compound non-volatile element at the time of writing data arewritten to the compound non-volatile element in the data writeoperation.

Therefore, data write operation to the compound ferroelectric capacitormay be utilized to perform logical calculation.

The logical calculation circuit of this invention is characterized bycomprising: a non-volatile memory element for retaining non-volatilestate corresponding to the first data to be calculated; a non-volatileload element for retaining non-volatile state of a different statechange rate depending on the first data to be calculated and connectedto the non-volatile memory element through a coupling node; and acalculation result output section for outputting a logical calculationresult of the first and second data to be calculated for a specifiedlogical operator based on the state change amount of both thenon-volatile memory element and the non-volatile load element obtainedby giving the second data to be calculated to the non-volatile memoryelement.

The logical calculation method of this invention is a method ofperforming logical calculation of the first and second data to becalculated for a specified logical operator, characterized bycomprising: a writing step of preparing a non-volatile memory elementfor retaining non-volatile state corresponding to the first data to becalculated and having the first and second terminals, and a non-volatileload element for retaining non-volatile state of different state changerate depending on the first data to be calculated and having the thirdterminal connected to the first terminal of the non-volatile memoryelement through the coupling node and the fourth terminal; and a readingstep of performing logical calculation based on the state change amountsof both the non-volatile memory element and the non-volatile loadelement obtained by connecting the fourth terminal of the non-volatileload element to a specified reference potential and by giving the seconddata to be calculated to the second terminal of the non-volatile memoryelement.

Therefore, according to the logical calculation circuit of thisinvention or the logical calculation method of this invention, anon-volatile memory element having stored a first data to be calculatedand a non-volatile load element for retaining non-volatile state ofdifferent state change rate depending on the first data to be calculatedare connected at a coupling node to form a compound non-volatileelement. When a second data to be calculated is given to thenon-volatile memory element forming the compound non-volatile capacitor,the state change amount of the compound non-volatile element is read asthe logical calculation result of the first and second data to becalculated for a specified logical operator.

Therefore, it is possible to perform logical calculation utilizing theoperation of reading data from the compound non-volatile element. Inother words, storage and logical calculation of data may be performedwith a single logical calculation circuit.

Further, it is possible to arrange that the state of the compoundnon-volatile element is greatly different corresponding to the logicalcalculation result at the time of reading data with a constitution inwhich the non-volatile state of the non-volatile load element isdifferent in the state change rate depending on the first data to becalculated. Therefore, data reading with a great margin is possible. Inother words, a logical calculation circuit is embodied that is capableof performing logical calculations at high speeds with high reliability.

The logical calculation circuit of this invention is characterized inthat the specified logical operator is determined by giving onereference potential chosen from two or more reference potentialscorresponding to two or more different logical operators to thenon-volatile load element prior to giving the second data to becalculated.

The logical calculation method of this invention is characterized inthat the specified reference potential is selectable from two or moredifferent reference potentials corresponding to two or more differentlogical operators, and the reading process includes the steps of: givingthe specified reference potential chosen to the fourth terminal of thenon-volatile load element and to the coupling node; and stopping givingthe specified reference potential to the coupling node while maintaininggiving the specified reference potential to the fourth terminal of thenon-volatile load element and, in that state, giving the second data tobe calculated to the second terminal of the non-volatile memory element.

Therefore, the logical calculation circuit of this invention or thelogical calculation method of this invention makes it possible toperform plural kinds of logical calculations using a single logicalcalculation circuit by the simple operation of choosing the specifiedreference potential in the data read operation.

The logical calculation circuit of this invention is characterized inthat the third and fourth data to be calculated are given to thenon-volatile memory element and to the non-volatile load element; andthe non-volatile states of the non-volatile memory element and thenon-volatile load element corresponding to the first data to becalculated is determined with the third and fourth data to be calculatedgiven and the non-volatile states of the non-volatile memory element andthe non-volatile load element before the third and fourth data to becalculated are given.

The logical calculation method of this invention is characterized inthat the writing step determines the new non-volatile states of thenon-volatile memory element and the non-volatile load elementcorresponding to the first data to be calculated by giving the thirddata to be calculated to the coupling node and by giving the fourth datato be calculated to both the second terminal of the non-volatile memoryelement and the fourth terminal of the non-volatile load element, andaccording to the third and fourth data to be calculated given and to thenon-volatile states of the non-volatile memory element and thenon-volatile load element before the third and fourth data to becalculated are given.

Therefore, according to the logical calculation circuit of thisinvention or the logical calculation method of this invention, a newfirst data to be calculated is determined with both the old first datato be calculated present as stored before writing data and the third andfourth data to be calculated given to the compound non-volatile elementat the time of writing data, and the new first data to be calculated iswritten to the compound non-volatile element by writing operation.

Therefore, it is possible to perform logical calculation utilizing thedata write operation to the compound non-volatile element.

The logical calculation circuit of this invention is characterized inthat the calculation result output section is an output transistor,having a control terminal connected to the coupling node and an outputterminal for outputting output signals corresponding to the controlsignal inputted to the control terminal, turning off when a potential asthe control signal nearer to the first reference potential than to thethreshold voltage of the output transistor is given and turning on whena potential as the control signal nearer to the second referencepotential than to the threshold voltage is given, and that the logicalcalculation result is obtained as the output signal of the outputtransistor.

Therefore, the output transistor turns off when the potential occurringat the coupling node in the data read operation is nearer to the firstreference potential than to the threshold voltage, and the outputtransistor turns on when the potential occurring at the coupling node inthe data read operation is nearer to the second reference potential thanto the threshold voltage. Therefore, it is possible to obtain thelogical calculation result as the output signal of the output transistorby appropriately setting the threshold voltage of the output transistor.

The logical calculation device of this invention is characterized inthat any of the above logical calculation circuits are arranged inseries and/or parallel to perform intended logical calculation.

Therefore, performing the intended logical calculations described aboveby combining a large number of the above-described logical calculationcircuits in which a single circuit serves both as the logicalcalculation section and the memory section, it is possible to reduceconsiderably the circuit area including the area required for wiring incomparison with conventional device in which the memory section isseparately provided. As a result, it is possible to greatly increase thedegree of integration of the device while reducing power consumption.

Further, because the memory is non-volatile, power for holding thememory is unnecessary. Therefore, power consumption for operating iskept down and little power is consumed when standing by. Moreover, abackup power source against possible power failure is also unnecessary.Furthermore, in the case a memory element including ferroelectriccapacitor is used as the non-volatile memory element, write operationmay be accelerated.

Moreover, using a large number of logical calculation circuits capableof reading data with large margin realizes a logical calculation devicecapable of performing logical calculations with high reliability at highspeeds.

The logical calculation device of this invention is characterized bycomprising: a search word holding section for holding a search word or asearch object, and a word circuit that holds a reference word or areference object, and for performing coincidence judgment between thereference word and the search word, and is made up of any of the abovelogical calculation circuits arranged in series and/or parallel to makecoincidence judgment of the reference word and the search word.

Therefore, it is possible to form a word circuit for performingcoincidence judgment of a reference word and a search word with a largenumber of the logical calculation circuits, each serving as both alogical calculation section and a memory section, combined together, toconsiderably reduce circuit area including the area required for wiringin comparison with conventional coincidence search devices. As a result,it is possible to greatly increase the degree of integration whilereducing power consumption.

Further, because the memory is non-volatile, power for holding thememory is unnecessary. Therefore, power consumption for operating iskept down and little power is consumed when standing by. Moreover, abackup power source against possible power failure is also unnecessary.Furthermore, in the case a memory element including ferroelectriccapacitor is used as the non-volatile memory element, write operationmay be accelerated.

Moreover, using a large number of logical calculation circuits capableof reading data with large margin realizes a logical calculation devicecapable of performing logical calculations with high reliability at highspeeds.

The logical calculation circuit of this invention is characterized inthat the word circuit, using a pair of logical calculation circuitsconnected in series for each bit forming a search word, obtains alogical value corresponding to the negation of an exclusive OR of thebit value of the reference word and the corresponding bit value of thesearch word, connects in parallel all the outputs of respective pairs ofthe logical calculation circuits to obtain a logical value correspondingto a logical product of all the logical values corresponding to thenegation of the exclusive OR calculated for each bit, and handles alogical value corresponding to the calculated logical product as acoincidence judgment output of the word circuit.

Therefore, it is possible to constitute that the coincidence output isproduced only when the reference word coincides completely with thesearch word. Therefore, it is possible to easily constitute acoincidence search device with a high degree of integration, low powerconsumption, high reliability, and high calculation speed, capable ofextracting only the reference word that coincides completely with thesearch word by carrying out coincidence judgment of the search word froma large number of reference words.

The logical calculation device of this invention is characterized bycomprising: a search word holding section for holding a search word or asearch object; and a word circuit made up of any of the logicalcalculation circuits arranged in series and/or parallel for holding areference word or a reference object as well as for performing magnitudecomparison judgment for the reference word and the search word.

Therefore, forming a word circuit for performing relative magnitudecomparison of the reference word and the search word by combiningtogether a large number of the above logical calculation circuits, eachserving both as a logical calculation section and a memory section,makes it possible to reduce considerably the circuit area including thearea required for wiring in comparison with conventional relativemagnitude comparison devices. As a result, it is possible to greatlyincrease the degree of integration of the device while reducing powerconsumption.

Further, because the memory is non-volatile, power for holding thememory is unnecessary. Therefore, power consumption for operating iskept down and little power is consumed in standby. Moreover, a backuppower source against possible power failure is also unnecessary.Furthermore, in the case a memory element including ferroelectriccapacitor is used as the non-volatile memory element, write operationmay be accelerated.

Moreover, using a large number of logical calculation circuits capableof reading data with large margin realizes a relative magnitudecomparison device capable of performing calculations with highreliability at high speeds.

The word circuit in the logical calculation device of this invention ischaracterized in that a plural number of logical calculation circuitsare used to produce a comparison decision output to the effect that thesearch word is greater than the reference word in the case the value ofat least one bit in question out of respective bits constituting thesearch word is greater than the value of a counterpart bit of thereference word, and the values of respective bits higher in positionthan the bit in question out of the respective bits constituting thesearch word are respectively equal to the values of respectivecounterpart bits of the reference word.

Therefore, it is possible to constitute so that a specific comparisonjudgment output is produced only when the search word is greater thanthe reference word. As a result, it is possible to easily constitute arelative magnitude comparison device with a high degree of integration,low power consumption, high reliability, and high calculation speed forextracting the only reference word smaller than the search word out of alarge number of reference words by performing relative magnitudecomparison judgment for a plural number of reference words and thesearch word.

The logical calculation device of this invention is a logicalcalculation device for performing addition of two or more pieces ofbinary numbers, characterized in that any of the above logicalcalculation circuits are arranged in series and/or parallel to performthe addition.

Therefore, constituting an adder with a combination of a large number ofthe above logical calculation circuits, each serving both as a logicalcalculation section and a memory section, makes it possible to reduceconsiderably the circuit area including the area required for wiring incomparison with conventional adders. As a result, it is possible toincrease the degree of integration of the device and keep down powerconsumption.

Further, because the memory is non-volatile, power for holding thememory is unnecessary. Therefore, power consumption in adding operationis kept down and little power is consumed when standing by. Moreover, abackup power source against possible power failure is also unnecessary.Furthermore, in the case a memory element including ferroelectriccapacitor is used as the non-volatile memory element, write operationmay be accelerated.

Further, using a large number of logical calculation circuits capable ofreading data with large margin makes it possible to realize an addercapable of performing adding operation with high reliability at highspeeds.

The logical calculation device of this invention is characterized inthat: the logical calculation includes addition of an augend and anaddend; the logical calculation device includes an addition resultcalculation section for calculating the addition result of the augendand the addend, and a carry information calculation section forcalculating carry information on the addition; the addition resultcalculation section using a plural number of logical calculationcircuits calculates the addition result according to the augend, addend,and carry information from a previous bit, and makes the addition resultobtained the output of the addition result calculation section; and thecarry information calculation section using a plural number of logicalcalculation circuits calculates the carry information for the bit inquestion according to the augend, addend, and carry information from theprevious bit, and makes the carry information obtained the output of thecarry information calculation section.

Therefore, it is possible to constitute a full adder using a pluralnumber of logical calculation circuits for calculating and storingaddition result and carry information. As a result, it is possible toeasily constitute a full adder with a high degree of integration, lowpower consumption, high reliability, and high calculation speed.

The logical calculation device of this invention is characterized inthat the device divides logical calculation into a plural number ofstages and implements the stages in sequence and that the deviceincludes any of the above logical calculation circuits arranged inseries and/or parallel to perform the logical calculation.

Therefore, constituting each stage with a large number of the abovelogical calculation circuits, each serving both as a logical calculationsection and a memory section, makes it possible to reduce considerablythe circuit area including the area required for wiring in comparisonwith conventional pipelined logical calculation devices. This makes itpossible to increase greatly the degree of integration and keep downpower consumption.

Further, because the memory is non-volatile, power for holding thememory is unnecessary. Therefore, power consumption in calculation iskept down and little power is consumed when standing by. Moreover, abackup power source against possible power failure is also unnecessary.Furthermore, in the case a memory element including ferroelectriccapacitor is used as the non-volatile memory element, write operationmay be accelerated.

Further, using a large number of logical calculation circuits capable ofreading data with large margin makes it possible to realize a pipelinedlogical calculation device capable of performing calculation with highreliability at high speeds.

The logical calculation device of this invention is characterized inthat the logical calculation includes addition of an augend and anaddend both being signed-digit binary numbers; the logical calculationdevice comprising: a first stage calculation section for performing,using a logical calculation circuit, a first stage calculation includingthe operations of calculating and storing two binary numberscorresponding to the augend and the addend; a second stage calculationsection for performing a second stage calculation, following the firststage calculation, including operations of calculating and storing onebinary number as a first addition result corresponding to the exclusiveOR of the two binary numbers using a pair of parallel-connected logicalcalculation circuits, and an operation of storing the first carryinformation for the bit in question calculated according to the augendand the addend using the logical calculation circuit; a third stagecalculation section for performing a third stage calculation, followingthe second stage calculation, including operations of calculating andstoring one binary number as a second addition result corresponding tothe exclusive OR of the first addition result and the first carryinformation from the previous bit using another pair of theparallel-connected logical calculation circuits, and operations ofcalculating and storing a second carry information for the bit inquestion according to the augend, the addend, and the first carryinformation from the previous bit using the logical calculation circuit;and a fourth stage calculation section for performing a fourth stagecalculation, following the third stage calculation, including operationsof calculating and storing a signed-digit binary number as an additionresult of the logical calculation device according to the secondaddition result and the second carry information from the previous bitusing a logical calculation circuit.

Therefore, it is possible to constitute a pipelined full adder capableof performing addition of signed-digit binary numbers, in which carrypropagation remains at a high bit only, by dividedly placing two pairsof logical calculation circuits for obtaining addition result and aplural number of logical calculation circuits for obtaining carryinformation in four stage calculation sections. This makes it possibleto easily constitute a pipelined full adder with high degree ofintegration, low power consumption, high reliability, and highcalculation speeds.

The logical calculation device of this invention is a logicalcalculation device for performing multiplication of two binary numberssequentially at plural divided levels, characterized by comprising: apartial product generating section for generating a signed-digit partialproduct corresponding to the partial product of a multiplicand and amultiplier; and an adder made by preparing a plural number of the abovelogical calculation devices as elementary calculation devices, disposingthem in a plural number of stages corresponding to respective levels toobtain a signed-digit binary number corresponding to the product of themultiplicand and the multiplier by performing sequential addition ofrespective stages using the signed-digit partial product and/or theprevious stage's addition result as inputs.

Therefore, it is possible to constitute a pipelined multiplier utilizingaddition of signed-digit binary numbers by disposing the above pipelinedfull adder as an elementary calculation device at a plural number ofstages corresponding to respective levels of multiplication. This makesit possible to easily constitute a pipelined multiplier with high degreeof integration, low power consumption, high reliability, and highspeeds.

In the logical calculation device of this invention, the partial productgenerating section generates signed-digit partial products about onefourth in number of bits of the multiplier based on the multiplicand andthe multiplier, and the addition section is constituted with a pluralnumber of elementary calculation devices connected in parallel to forman addition unit capable of adding two signed-digit partial products,with one or more of the addition units disposed in each levelcalculation device for performing calculation at each level.

The first level calculation device for performing the first levelcalculation, using a plural number of addition units connected inparallel, performs addition of inputs or signed-digit partial productsto obtain the first level addition results substantially half in numberof the total number of the signed-digit partial products generated inthe partial product generating section, and stores the results.

Each intermediate level calculation section for performing calculationof the intermediate level, using a plural number of addition unitsconnected in parallel, performs addition of inputs or the additionresults of the previous level to obtain the addition results of theintermediate level substantially half in number of the previous level.

The final level calculation section for performing the final levelcalculation is characterized in that it uses one addition unit, performsaddition of inputs or the addition results of the previous level toobtain one addition result of the final level and stores the obtainedaddition result of the final level as a signed-digit binary numbercorresponding to the above-mentioned product of the multiplicand and themultiplier.

Therefore, it is possible to obtain a data corresponding to the productof a multiplicand and a multiplier with a limited number of levels bygenerating signed-digit partial products about one fourth in number ofthe number of multiplier bits and repeating the operation of halving theobtained signed-digit partial products at each level. This makes itpossible to easily constitute a pipelined multiplier capable ofperforming multiplication utilizing the addition of signed-digit binarynumbers with high degree of integration, low power consumption, highreliability, and high speeds.

The logical calculation device of this invention is characterized inthat the logical calculation includes the addition of three binarynumbers: an augend, an addend, and a carry from a lower bit; and thatthe logical calculation device includes: a first addition stagecalculation section for performing, using a pair of theparallel-connected logical calculation circuits, a first stage additioncalculation including the operations of calculating and storing a binarynumber as a first addition result corresponding to an exclusive OR ofbinary numbers corresponding to two out of three binary numbers; and asecond addition stage calculation section for performing, following thefirst addition stage calculation, a second addition stage calculationincluding operations of calculating and storing a binary number as asecond addition result corresponding to a binary number corresponding toan exclusive OR of the first addition result and the remaining one ofthe three binary numbers and outputting the second addition result as anaddition result of the logical calculation device using another pair ofthe parallel-connected logical calculation circuits, and an operation ofoutputting a carry in the addition of the three binary numbers accordingto the three binary numbers using a plural number of the logicalcalculation circuits.

Therefore, it is possible to constitute a pipelined full adder bydividedly disposing two pairs of logical calculation circuits forcalculating an addition result and a plural number of logicalcalculation circuits in two stage calculation sections. Therefore, itpossible to easily constitute a pipelined full adder with high degree ofintegration, low power consumption, high reliability, and highcalculation speeds.

The logical calculation device of this invention is the one forperforming the multiplication of two binary numbers sequentially in aplural number of divided levels and includes: a partial productgenerating section for generating the partial product of a multiplicandand a multiplier, and an addition section formed with a plural number ofthe above logical calculation devices prepared as elementary calculationdevices and disposing them in a plural number of stages corresponding tothe respective levels for obtaining a calculation result by sequentiallyperforming additions of respective stages using the partial productand/or the addition result of the previous stage as inputs.

Therefore, it is possible to constitute a pipelined multiplier bydisposing the above pipelined full adders as elementary calculationdevices in a plural number of stages corresponding to the respectivelevels of the multiplication. Therefore, it is possible to easilyconstitute a pipelined multiplier with high degree of integration, lowpower consumption, high reliability, and high operation speeds.

In the logical calculation device of this invention, the plural numberof levels correspond in number to at least the number of multiplierbits, the partial product generating section is constituted withelementary product generating sections disposed in respective levelcalculation sections for performing calculation in respective levels,and the addition section is constituted with elementary calculationdevices disposed in respective level calculation sections for performingcalculations at least in the second and later levels.

Further, each level calculation section for performing the calculationsat least from the second level includes: the first stage calculationsection for performing the first stage calculation including anoperation of storing one bit, the current calculation object, out ofplural bits constituting the multiplicand, as a calculation object bitof the multiplicand; the second stage calculation section for performingthe second stage calculation, using the elementary partial productgenerating section, following the first stage calculation, includingoperations of calculating and storing a logical product of thecalculation object bit of the multiplicand and a bit, corresponding tothe relevant level, out of plural bits constituting the multiplier, asthe elementary partial product at the relevant level of the relevantcalculation object bit of the multiplicand; and the third and fourthstage calculation sections for performing the third and fourth stagecalculations, using the elementary calculation device, following thesecond stage calculation, including operations of calculating a sum ofthree binary numbers, the elementary partial product at the relevantlevel, the partial product at the previous level, and the carry at therelevant level for the bit before the relevant calculation object bit ofthe multiplicand and storing the sum as the partial product at therelevant level for the relevant calculation object bit of themultiplicand, and an operation of storing the carry produced here as thecarry at the relevant level of the relevant calculation object bit ofthe multiplicand.

Therefore, it is possible to constitute a pipelined multiplier ofseries-parallel type by giving respective bit values of the multiplierin advance to the corresponding level calculation sections the same innumber as the number of the multiplier bits, sequentially givingrespective bit values of the multiplicand to the first level calculationsection, and sequentially giving respective bit values of themultiplicand from the previous level calculation section with aspecified delay to the intermediate level calculation section.Therefore, it is possible to easily constitute a pipelined multiplier ofseries-parallel type with high degree of integration, low powerconsumption, high reliability, and high speed calculation.

Incidentally, the term “state change rate” used in Claims means theextent of change in the state of non-volatile memory element andnon-volatile load element caused by giving the second data to becalculated.

Unless specifically mentioned, negation (inversion signal) of a binarynumber (binary signal) “A” is to be expressed with “/A.”

While this invention is described above by means of preferableembodiments, respective terms are used not for restriction but forexplanation, and therefore may be changed within the scope of appendedClaims without departing from the scope and spirit of this invention.

1. A logical calculation circuit comprising: a storage ferroelectriccapacitor for retaining a polarized state corresponding to a first datato be calculated and having a first and a second terminals; a loadferroelectric capacitor for retaining a polarized state in substantiallycomplementary relationship to the polarized state of the storageferroelectric capacitor, having a third terminal connected to the firstterminal of the storage ferroelectric capacitor, and a fourth terminal;and a calculation result output section connected to a coupling nodebetween the first terminal of the storage ferroelectric capacitor andthe third terminal of the load ferroelectric capacitor to output alogical calculation result of the first data to be calculated and asecond data to be calculated for a specified logical operator based onthe potential of the coupling node obtained by connecting the fourthterminal of the load ferroelectric capacitor to a specified referencepotential while giving the second data to be calculated to the secondterminal of the storage ferroelectric capacitor.
 2. The logicalcalculation circuit of claim 1, wherein the specified referencepotential is selectable from two or more different reference potentialscorresponding to two or more different logical operators, and thespecified logical operator is determined by connecting the chosenspecified reference potential to the fourth terminal of the loadferroelectric capacitor while pre-charging the coupling node to thespecified reference potential before giving the second data to becalculated.
 3. The logical calculation circuit of claim 1 or 2, whereinthe coupling node is given a third data to be calculated; the secondterminal of the storage ferroelectric capacitor and the fourth terminalof the load ferroelectric capacitor are given a fourth data to becalculated, and the polarized states of the storage ferroelectriccapacitor and the load ferroelectric capacitor corresponding to thefirst data to be calculated are determined with both the third andfourth data to be calculated given and the polarized states of thestorage ferroelectric capacitor and the load ferroelectric capacitorbefore the third and fourth data are given.
 4. A logical calculationcircuit comprising: a non-volatile memory element for retainingnon-volatile state corresponding to a first data to be calculated s as abinary data, and having first and second terminals; a non-volatile loadelement for retaining non-volatile state corresponding to the inverteddata/s of the first data to be calculated s, and having a third terminalconnected to the first terminal of the non-volatile memory element, anda fourth terminal; and a calculation result output section foroutputting a logical calculation result of the first and a second datato be calculated s and x, as a calculation result data z as a binarydata, for a specified logical operator corresponding to a referencepotential arbitrarily chosen out of two complementary referencepotentials, according to the states of the non-volatile memory elementand the non-volatile load element obtained by pre-charging the couplingnode of the first terminal of the non-volatile memory element and thethird terminal of the non-volatile load element with the referencepotential and then giving the second data x as a binary data, to thesecond terminal of the non-volatile memory element while maintaining thefourth terminal of the non-volatile load element at the referencepotential, wherein the calculation result data z substantially meets thefollowing equation when the binary data corresponding to the twocomplementary reference potentials are assumed to be c and /c,z=/c AND x AND /s OR c AND (x OR /s).
 5. The logical calculation circuitof claim 4, wherein the first data s to be calculated corresponds to anew non-volatile state of the non-volatile memory element obtained bygiving a third data y1 as a binary data to the coupling node whilegiving a fourth data y2 as a binary data to both the second terminal ofthe non-volatile memory element and the fourth terminal of thenon-volatile load element, and substantially meets the followingequation when the first data before the third and fourth data are givenis assumed to be sb,s=/sb AND /y1 AND y2 OR sb AND (/y1 OR y2).
 6. A logical calculationcircuit comprising: a non-volatile memory element for retainingnon-volatile state corresponding to a first data to be calculated, anon-volatile load element for retaining non-volatile state of differentrate of change depending on the first data to be calculated, connectedto the non-volatile memory element at a coupling node; and a calculationresult output section for outputting a logical calculation result of thefirst and second data to be calculated for a specified logical operatoraccording to the state change amounts, of both the non-volatile memoryelement and the non-volatile load element, obtained by giving a seconddata to be calculated to the non-volatile memory element.
 7. The logicalcalculation circuit of claim 6, wherein the specified logical operatoris determined by giving a reference potential chosen out of two or moredifferent reference potentials corresponding to two or more differentlogical operators to the non-volatile load element before giving thesecond data to be calculated.
 8. The logical calculation circuit ofclaim 6 or 7, wherein the third and fourth data to be calculated aregiven to both the non-volatile memory element and the non-volatile loadelement; and the non-volatile states of the non-volatile memory elementand the non-volatile load element corresponding to the first data to becalculated are determined with the third and fourth data to becalculated and the non-volatile states of the non-volatile memoryelement and the non-volatile load element before the third and fourthdata to be calculated are given.
 9. The logical calculation circuit ofone of claims 1, 4, or 6, wherein the calculation result output sectioncomprises an output transistor having a control terminal connected tothe coupling node and an output terminal for outputting signalscorresponding to control signals inputted to the control terminal, andturning off when a potential as the control signal nearer to the firstreference potential than to the threshold voltage of the outputtransistor is given and turning on when a potential nearer to the secondreference potential than to the threshold voltage is given, and thelogical calculation result is obtained as the output signal of theoutput transistor.
 10. A logical calculation device constituted toperform specified logical calculations with any of the logicalcalculation circuits of claims 1, 4, or 6 disposed in series and/orparallel.
 11. A logical calculation device comprising: a search wordholding section for holding a search word as an object of search, and aword circuit for holding a reference word as an object of reference, andfor performing coincidence judgment between the reference word and thesearch word, constituted by disposing any of the logical calculationcircuits of claim 1, 4, or 6 in parallel and/or series.
 12. The logicalcalculation device of claim 11, wherein the word circuit, using a pairof the logical calculation circuits connected in series for respectivebits constituting the reference word, calculates a logical valuecorresponding to the negation of exclusive OR of the bit value of thereference word and the bit value of the search word, calculates alogical value corresponding to the logical product of the entire logicalvalues corresponding to the negation of exclusive OR calculated for eachbit by connecting all the outputs of the pair of logical circuits inparallel, and makes a logical value corresponding to the calculatedlogical product a coincidence judgment output of the word circuit.
 13. Alogical calculation device comprising: a search word holding section forholding a search word as an object of search; and a word circuit forholding a reference word and performing magnitude comparison judgmentbetween the reference word and the search word, constituted by disposingany of the logical calculation circuits of claim 1, 4, or 6 in paralleland/or series to perform the reference word holding and the magnitudecomparison judgment.
 14. The logical calculation circuit of claim 13,wherein the word circuit, using a plural number of the logicalcalculation circuits, produces a comparison decision output to theeffect that the search word is greater than the reference word in thecase the value of at least one bit in question out of respective bitsconstituting the search word is greater than the value of a counterpartbit of the reference word, and the values of respective bits higher inposition than the bit in question out of the respective bitsconstituting the search word are respectively equal to the values ofrespective counterpart bits of the reference word.
 15. A logicalcalculation device for performing addition of two or more pieces ofbinary numbers, constituted with any of the logical calculation circuitsof claim 1, 4 or 6 in series and/or parallel to perform the addition.16. The logical calculation device of claim 15, wherein the logicalcalculation includes addition of an augend and an addend; the logicalcalculation device comprises an addition result calculation section forcalculating the addition result of the augend and the addend, and acarry information calculation section for calculating carry informationon the addition; the addition result calculation section using a pluralnumber of the logical calculation circuits calculates the additionresult according to the augend, addend, and carry information from aprevious bit, and makes the addition result obtained the output of theaddition result calculation section; and the carry informationcalculation section, using a plural number of logical calculationcircuits, calculates the carry information for the bit in questionaccording to the augend, addend, and carry information from the previousbit, and makes the carry information obtained the output of the carryinformation calculation section.
 17. A logical calculation device forperforming logical calculation in sequence of a plural number of dividedstages with any of the logical calculation circuits of claim 1, 4 or 6disposed in series and/or parallel.
 18. The logical calculation deviceof claim 15, wherein the logical calculation includes addition of anaugend and an addend, both signed-digit binary numbers; the logicalcalculation device comprising: a first stage calculation section forperforming, using the logical calculation circuit, a first stagecalculation including the operations of calculating and storing twobinary numbers corresponding to the augend and the addend; a secondstage calculation section for performing a second stage calculation,following the first stage calculation, including operations ofcalculating and storing one binary number as a first addition resultcorresponding to the exclusive OR of the two binary numbers using a pairof parallel-connected logical calculation circuits, and an operation ofstoring the first carry information for the bit in question calculatedaccording to the augend and the addend using the logical calculationcircuit; a third stage calculation section for performing a third stagecalculation, following the second stage calculation, includingoperations of calculating and storing one binary number as a secondaddition result corresponding to the exclusive OR of the first additionresult and the first carry information from the previous bit usinganother pair of the parallel-connected logical calculation circuits, andoperations of calculating and storing a second carry information for thebit in question according to the augend, the addend, and the first carryinformation from the previous bit using the logical calculation circuit;and a fourth stage calculation section for performing a fourth stagecalculation, using the logical calculation circuit, following the thirdstage calculation, including operations of calculating and storing asigned-digit binary number as an addition result of the logicalcalculation device according to the second addition result and thesecond carry information from the previous bit.
 19. A logicalcalculation device for performing multiplication of two pieces of binarynumbers in sequence of a plural number of divided levels, comprising: apartial product generating section for generating a signed-digit partialproduct corresponding to the partial product of a multiplicand and amultiplier; and an adder made by preparing a plural number of thelogical calculation devices of claim 18 as elementary calculationdevices, disposing them in a plural number of stages corresponding torespective levels to obtain the signed-digit binary number correspondingto the product of the multiplicand and the multiplier by performingsequential addition of respective stages using the signed-digit partialproduct and/or the addition result of the previous stage as inputs. 20.The logical calculation device of claim 19, wherein the partial productgenerating section, according to the multiplicand and multiplier,generates signed-digit partial products about one fourth in number ofbits of the multiplier; the addition section is constituted with aplural number of the elementary calculation devices connected inparallel to form an addition unit capable of performing addition of twopieces of the signed-digit partial products, with one or more pieces ofthe addition units disposed at each level calculation section forperforming calculation at each level; the first level calculationsection for performing the first level calculation, using a pluralnumber of the addition units disposed in parallel, performs operationsof addition using the signed-digit partial products as inputs andstoring the addition results at the first level substantially half innumber of the total number of the signed-digit partial productsgenerated in the partial product generating section; each ofintermediate level calculation sections for performing calculation ofthe intermediate level, using a plural number of addition unitsconnected in parallel, perform addition of inputs, the addition resultsof the previous level, to obtain the addition results of theintermediate level substantially half in number of the previous level;and final level calculation unit for performing the final levelcalculation, using one addition unit, performs addition of inputs, theaddition results of the previous level, to obtain one addition result ofthe final level and stores the obtained addition result of the finallevel as a signed-digit binary number corresponding to the product ofthe multiplicand and the multiplier.
 21. The logical calculation deviceof claim 15, wherein the logical calculation includes the addition ofthree binary numbers: an augend; an addend; and a carry from a lowerbit; and the logical calculation device comprises: a first additionstage calculation section for performing, using a pair of theparallel-connected logical calculation circuits, a first stage additioncalculation including operations of calculating and storing a binarynumber as a first addition result corresponding to an exclusive OR ofbinary numbers corresponding to two out of three binary numbers; and asecond addition stage calculation section for performing, following thefirst addition stage calculation, a second addition stage calculationincluding operations of calculating and storing a binary number as asecond addition result corresponding to a binary number corresponding toan exclusive OR of the first addition result and the remaining one ofthe three binary numbers and outputting the second addition result as anaddition result of the logical calculation device using another pair ofthe parallel-connected logical calculation circuits, and an operation ofoutputting a carry in the addition of the three binary numbers accordingto the three binary numbers using a plural number of the logicalcalculation circuits.
 22. A logical calculation device for performingmultiplication of two pieces of binary numbers in sequence of a pluralnumber of divided levels, comprising: a partial product generatingsection for generating the partial product of a multiplicand and amultiplier; and an addition section formed with a plural number of thelogical calculation devices of claim 21 prepared as elementarycalculation devices and disposing them in a plural number of stagescorresponding to the respective levels for obtaining a calculationresult by sequentially performing additions of respective stages usingthe partial product and/or the addition result of the previous stage asinputs.
 23. The logical calculation device of claim 22, wherein theplural number of levels correspond in number at least to the number ofbits of the multiplier; the partial product generating section isconstituted with elementary partial product generating sections disposedin respective level calculation sections performing calculation inrespective levels; and the addition section is constituted withelementary calculation devices disposed in respective level calculationsections for performing calculations at least in the second and laterlevels; each of the level calculation sections for performing thecalculations at least in the second and later levels comprises: a firststage calculation section for performing the first stage calculationincluding an operation of storing one bit as the current calculationobject, out of plural bits constituting the multiplicand, as acalculation object bit of the multiplicand; a second stage calculationsection for performing the second stage calculation, using theelementary partial product generating section, following the first stagecalculation, including operations of calculating and storing a logicalproduct, of the calculation object bit of the multiplicand and a bit,corresponding to the relevant level, out of plural bits constituting themultiplier, as the elementary partial product at the relevant level ofthe relevant calculation object bit of the multiplicand; and third andfourth stage calculation sections for performing the third and fourthstage calculations, using the elementary calculation device, followingthe second stage calculation, including operations of calculating a sumof three binary numbers: the elementary partial product at the relevantlevel, the partial product at the previous level, and the carry at therelevant level for the bit before the relevant calculation object bit ofthe multiplicand and storing the sum as the partial product at therelevant level for the relevant calculation object bit of themultiplicand, and an operation of storing the carry produced in thisaddition as the carry at the relevant level of the relevant calculationobject bit of the multiplicand.
 24. A method of performing logicalcalculation of first and second data to be calculated for a specifiedlogical operator, comprising: a writing step of preparing a non-volatilememory element for retaining non-volatile state corresponding to thefirst data to be calculated and having the first and second terminals,and a non-volatile load element for retaining non-volatile state ofdifferent state change rate depending on the first data to becalculated, and having the third terminal connected to the firstterminal of the non-volatile memory element through the coupling node,and the fourth terminal; and a reading step of performing logicalcalculation based on the state change amounts of both the non-volatilememory element and the non-volatile load element obtained by connectingthe fourth terminal of the non-volatile load element to a specifiedreference potential and by giving the second data to be calculated tothe second terminal of the non-volatile memory element.
 25. The logicalcalculation method of claim 24, wherein the specified referencepotential is selectable from two or more different reference potentialscorresponding to two or more different logical operators; and thereading process comprises the steps of: giving the specified referencepotential chosen to both the fourth terminal of the non-volatile loadelement and the coupling node; and stopping giving the specifiedreference potential to the coupling node while maintaining giving thespecified reference potential to the fourth terminal of the non-volatileload element and, in that state, giving the second data to be calculatedto the second terminal of the non-volatile memory element.
 26. Thelogical calculation method of claim 24 or 25, wherein the writing stepdetermines new non-volatile states of the non-volatile memory elementand the non-volatile load element corresponding to the first data to becalculated by giving the third data to be calculated to the couplingnode and by giving the fourth data to be calculated to both the secondterminal of the non-volatile memory element and the fourth terminal ofthe non-volatile load element, and according to the third and fourthdata to be calculated given and to the non-volatile states of thenon-volatile memory element and the non-volatile load element before thethird and fourth data to be calculated are given.